OPENMP ANALYSIS IN VTUNE AMPLIFIER XE
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The document outlines the VTune Amplifier XE OpenMP analysis, focusing on addressing customer questions regarding OpenMP application performance. It discusses typical issues such as parallelization inefficiency, scalability, and insights into profiling OpenMP regions to identify performance bottlenecks. The analysis utilizes a combination of tracing and sampling technologies and is designed to be effective for many-core systems, aiding in the optimization of MPI + OpenMP hybrid applications.
OPENMP ANALYSIS IN VTUNE AMPLIFIER XE
- 2. Copyright © 2017, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. Optimization Notice 2 Agenda • VTune Amplifier XE OpenMP* Analysis: answering on customers’ questions about performance in the same language a program was written in • Concepts, metrics and technology inside • VTune Amplifier XE OpenMP Analysis Workflow • OpenMP analysis for hybrid MPI + OpenMP applications • Summary
- 3. Copyright © 2017, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. Optimization Notice 3 Typical customer questions on parallelization efficiency of OpenMP* applications • “I put pragmas but why my speed up is far from linear? • Parallelization inefficiency • “I ran my app on a system with bigger number of cores but it does not run as efficient as on smaller number” • Scalability issues • Is serial time of my application significant to prevent scaling? • How efficient is my OpenMP parallelization? • If not, how much gain can be achieved if I invest in fighting with the inefficiencies? • What OpenMP regions/loops/barriers are worth to tune? • What are the particular problems with them? Decomposing the questions
- 4. Copyright © 2017, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. Optimization Notice 4 If Performance Information is OpenMP “Unaware”.. OpenMP “unaware” views of VTune Amplifier XE Difficult to detect problems, customers might even “blame” runtime seeing CPU time consumption there not understanding that this is a result of parallelization inefficiency The questions are tied to OpenMP program structure – #pragmas Answers should be given the same way to be understandable and actionable
- 5. Copyright © 2017, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. Optimization Notice Is serial time of my application significant to prevent scaling? How efficient is my parallelization towards ideal parallel execution? How much theoretical gain I can get if invest in tuning? What regions are more perspective to invest? Links to grid view for more details on inefficiency 5 VTune Amplifier XE OpenMP* Analysis: answering on customers’ questions about performance in the same language a program was written in Overview on summary pane
- 6. Copyright © 2017, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. Optimization Notice 6 Key of OpenMP awareness in VTune – Region based views and metrics Definition of Region Potential Gain (elapsed time metric) Lock spinning (sampling) Effective time (sampling) Imbalance (tracing) Actual Parallel Region Elapsed Time Estimated Ideal Time = Effective time / Number of Threads Potential Gain as a sum of inefficiencies normalized by num of threads Fork Join Scheduling (sampling) Work forking (sampling) Atomics (sampling)
- 7. Copyright © 2017, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. Optimization Notice 7 Technology under VTune Amplifier XE OpenMP Analysis Tracing of OpenMP constructions to provide region/work sharing context and precise imbalance on barriers • Provided to VTune by Intel OpenMP Runtime under profiling • Fork-Join points of parallel regions with number of working threads (Intel Compiler 14 and later) • OpenMP construct barrier points with imbalance info and OpenMP loop metadata • -parallel-source-info=2 compiler option to embed source file name to a region name • Looking at transition to OMPT, working with John M.-C. on interface enrichments for low overhead analysis Sampling to define and classify CPU time - user’s code and OpenMP RTL work • Classification: Locking, Scheduling, Work Forking
- 8. Copyright © 2017, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. Optimization Notice 8 VTune Amplifier XE OpenMP Analysis Workflow Start with HPC Performance Characterization analysis Explore CPU Utilization aspect metrics related to OpenMP in summary, grid, source view CL: >amplxe-cl –collect hpc-performance <my_app>
- 9. Copyright © 2017, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. Optimization Notice 9 Per Region Details in grid view: inefficiencies in wall time - classification and issue highlighting Imbalance on a loop barrier Dynamic scheduling overhead on a parallel loop
- 10. Copyright © 2017, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. Optimization Notice 10 Details in Grid View: Serial Time Hotspots Serial hotspots under Master Thread Time Filter to exclude initialization phase
- 11. Copyright © 2017, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. Optimization Notice 11 Details on Scalable Timeline Super tiny timeline display mode – a bird-eye’s view having all data without scrolling Intel® Xeon Phi™ profiling result with 288 threads Region frames on the ruler More green color – more efficient multithreaded execution
- 12. Copyright © 2017, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. Optimization Notice 12 Details for a Region at source file level
- 13. Copyright © 2017, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. Optimization Notice 13 Summary • VTune Amplifier XE OpenMP analysis answers on customer’s questions about performance on the language of OpenMP constructs • The analysis is well-scalable for many-core systems with good balance of tracing and sampling collection technologies • The OpenMP analysis is “MPI-aware” that is helpful for inner-node hybrid MPI + OpenMP application tuning • The full feature set is available in VTune Amplifier XE 2018 with Intel OpenMP and Intel MPI runtimes as a part of Intel® Parallel Studio XE 2018
- 14. 14 Back-up
- 15. 15 A Use Case: NPB CG imbalance improvement • Step 1: Profiling original application – NPB CG (Class B) There is a region with promising potential gain – go to Grid View for more details
- 16. 16 A Use Case: NPB CG imbalance improvement • Step 1: Profiling original application – NPB CG (Class B) • There are barriers in region – use experimental “/OpenMP Region/OpenMP Barrier..” grouping • Imbalance on omp loop in cg.f, lines: 572 - 580, schedule is static
- 17. 17 A Use Case: NPB CG imbalance improvement • Step 2: Trying dynamic scheduling omp do schedule (dynamic) Elapsed time increased – no improvement Go to Grid View for details
- 18. 18 A Use Case: NPB CG imbalance improvement • Step 2: Trying dynamic scheduling “omp do schedule (dynamic)” Default chunk size is 1 and it led to scheduling overhead Let’s try bigger chunk size
- 19. 19 A Use Case: NPB CG imbalance improvement • Step 3: Trying dynamic schedule with chunk 20 Improved original elapsed time ~15%, eliminated imbalance
- 21. Legal Disclaimer & Optimization Notice INFORMATION IN THIS DOCUMENT IS PROVIDED “AS IS”. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO THIS INFORMATION INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. Copyright © 2017, Intel Corporation. All rights reserved. Intel, Pentium, Xeon, Xeon Phi, Core, VTune, Cilk, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. Optimization Notice Intel’s compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804 21