Operation of 8255A
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The 8255A Programmable Peripheral Interface chip has two main modes of operation - I/O mode and Bit Set-Reset mode. In I/O mode, the ports work as programmable I/O ports and can be configured in three sub-modes (Mode 0, 1, and 2) using a Control Word Register. Mode 1 uses handshaking signals to coordinate data transfer between ports. Mode 2 allows bi-directional communication on a single bus. In Bit Set-Reset mode, individual bits of port C can be set or reset using the Control Word Register.
![Mode 1 (STROBE I/O)
ā¢ This functional configuration provides a means for
transferring I/O data to or from a specified port in conjunction
with strobes or āhandshakingā signals.
ā¢ In mode 1, Port A and Port B use the lines on Port C to
generate or accept these āhandshakingā signals.
PC4
PC5
PC3
8255A
I/P
PC2
PC1
PC0
PC6,7
PA[0:7]
STB(A)[AL]
IBF(A)
INTR(A)
PB[0:7]
STB(B)[AL]
IBF(B)
INTR(B)
O/P
PC7
PC6
PC3
8255A
anuj_yadav
PC2
PC1
PC0
PC4,5
PA[0:7]
OBF(A)[AL]
ACK(A)[AL]
INTR(A)
PB[0:7]
OBF(B)[AL]
ACK(B)[AL]
INTR(B)
8](https://image.slidesharecdn.com/operationof8255a-131109234206-phpapp02/85/Operation-of-8255A-8-320.jpg)
![Mode 2
(STROBE BIDIRECTIONAL BUS I/O)
ā¢ This functional configuration provides a means for
communicating with a peripheral device or structure on a
single 8-bit bus for both transmitting and receiving data
(bidirectional bus I/O).
ā¢ āHandshakingā signals are provided to maintain proper bus
flow discipline in a similar manner to MODE 1.
ā¢ Interrupt generation and enable/disable functions are also
available.
PA[0:7]
8255A
PC7
STB(A)[AL]
PC6
IBF(A)
INTR(A)
PC4
PC5
INTR(A)
PC3
INTR(A)
PC2
PC1
PC0
anuj_yadav
PB[0:7]
10](https://image.slidesharecdn.com/operationof8255a-131109234206-phpapp02/85/Operation-of-8255A-10-320.jpg)
Operation of 8255A
- 1. OPERATION OF 8255A PROGRAMMABLE PERIPHERAL INTERFACE BY : ANUJ YADAV 14606, ECS anuj_yadav 1
- 2. MODES There are two basic modes of operation of 8255A. ā¢ I/O mode ā In this mode, the 8255A ports work as programmable I/O ports. ā¢ Bit Set-Reset mode ā In this mode, only port C (PC0 ā PC7) can be used to set or reset its individual port bits. anuj_yadav 2
- 3. Bit Operation D7 1 for I/O Mode | 0 for BSR Mode D6, D5, D4 These are Undefined or Donāt Care D3, D2, D1 These are Bit select flags 000-111 => for bits PC0 ā PC7 D0 1 for set | 0 for Reset ā¢ I/O Mode Control Word Register Format ā The I/O modes can be programmed using control word register by putting D7 at logic 1. Format is shown below: D7 D6 D5 D4 D3 D2 D1 D0 1 X X X B2 B1 B0 S/R ā¢ Bit Set-Reset Mode ā In this mode any of the 8-bits of port C can be set or reset depending on D0 of the control word. The bit to be set or reset is selected by bit select flags D3, D2 and D1 of CWR. Format is shown below: D7 D6 D5 D4 D3 D2 D1 D0 0 X X X B2 B1 B0 S/R anuj_yadav 3
- 4. HANDSHAKING Signals ā¢ Dedicated lines used to coordinate data transfer. ā¢ Used to signal ready/not ready, or to acknowledge or request. NEED: ā¢ The MPU and peripherals operate at different speeds, the MPU being faster than the peripherals. ā¢ To avoid overlapping of data during data input or data output, handshake signals are used between MPU & the peripherals. anuj_yadav 4
- 5. I/O Operating Modes ā¢ Under the I/O mode of operation, further there are three modes of operation of 8255A. ļ Mode 0 ā Basic Input/output ļ Mode 1 ā Strobed Input/output ļ Mode 2 ā Bi-directional Bus ā¢ All these modes can be selected by programming register internal to 8255A known Control Word Register(CWR). ā¢ This very register with different format can also be used for Bit Set-Reset(BSR) mode of Operation. anuj_yadav 5
- 6. Mode 0 (BASIC I/O) ā¢ Provides simple input and output capabilities using each of the three ports. ā¢ Data can be simply read from and written to the input and output ports respectively, after appropriate initialization. ā¢ No Handshaking is required. PA 8255A PA6-PA7 PA PCU PC4-PC7 PCU PCL PC0-PC3 PB PB0-PB7 8255A PA PC PCL PB PB0-PB7 Signals in MODE 0 anuj_yadav 6
- 7. ā¢ ā¢ ā¢ ā¢ ā¢ Features of mode 0: Two 8-bits and two 4-bits ports. Output ports are latched. Input ports are buffered, not latched. Any port can be input or output. With 4 ports, 16 different combinations of I/O are possible. anuj_yadav 7
- 8. Mode 1 (STROBE I/O) ā¢ This functional configuration provides a means for transferring I/O data to or from a specified port in conjunction with strobes or āhandshakingā signals. ā¢ In mode 1, Port A and Port B use the lines on Port C to generate or accept these āhandshakingā signals. PC4 PC5 PC3 8255A I/P PC2 PC1 PC0 PC6,7 PA[0:7] STB(A)[AL] IBF(A) INTR(A) PB[0:7] STB(B)[AL] IBF(B) INTR(B) O/P PC7 PC6 PC3 8255A anuj_yadav PC2 PC1 PC0 PC4,5 PA[0:7] OBF(A)[AL] ACK(A)[AL] INTR(A) PB[0:7] OBF(B)[AL] ACK(B)[AL] INTR(B) 8
- 9. ā¢ ā¢ ā¢ ā¢ Features of mode 1: Two Groups (Group A and Group B). Each group contains one 8-bit data port and one 4-bit control/data port. The 8-bit data port can be either input or output. Both inputs and outputs are latched. The 4-bit port is used for control and status of the 8-bit data port. PC0 ā PC2 for Port B and PC3 ā PC5 for Port A. anuj_yadav 9
- 10. Mode 2 (STROBE BIDIRECTIONAL BUS I/O) ā¢ This functional configuration provides a means for communicating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bidirectional bus I/O). ā¢ āHandshakingā signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1. ā¢ Interrupt generation and enable/disable functions are also available. PA[0:7] 8255A PC7 STB(A)[AL] PC6 IBF(A) INTR(A) PC4 PC5 INTR(A) PC3 INTR(A) PC2 PC1 PC0 anuj_yadav PB[0:7] 10
- 11. ā¢ Features of mode 1: ā¢ Used in Group A only. ā¢ One 8-bit, bi-directional bus port (Port A) and a 5-bit control port (Port C). ā¢ Three I/O lines available at port C. ā¢ Both inputs and outputs are latched. ā¢ The 5-bit control port (Port C) is used for control and status for the 8-bit, bi-directional bus port (Port A). anuj_yadav 11