Parallel Adder_Mul_Mag.pptx

BECE102L – Digital System
Design
Dr.Vydeki D
Associate Professor Senior/ SENSE
VIT Chennai

PARALLEL ADDER
 A single full adder is capable of adding two one bit
numbers and an input carry. In order to add a binary
number with more than one bit an additional full
adders must be employed.
 The n-bit parallel adder can be constructed using “n”
number of full adder circuits in parallel.
 The block diagram of n-bit parallel adder using
number of full adder circuits connected in cascade
i.e. the carry output of each adder is connected to the
carry input of the next higher order adder is shown in
figure.

PARALLEL ADDER
n-bit parallel Adder

PARALLEL ADDER
 The 4-bit binary adder using full adder circuits is
capable of adding two 4-bit numbers resulting in a
4-bit sum and a carry output as shown in figure
below.
4-bit binary parallel Adder

PARALLEL ADDER
 Since all the bits of augend and addend are fed
into the adder circuits simultaneously and the
additions in each position are taking place at the
same time, this circuit is known as parallel adder.
 Let the 4-bit words to be added be represented
by, A3 A2 A1 A0= 1 1 1 1 and B3 B2 B1 B0= 0 0 1 1.

PARALLEL ADDER
Logic diagram of 4-bit parallel adder

PARALLEL ADDER
 The bits are added with full adders, starting from
the least significant position, to form the sum bit
and carry bit.
 The input carry C0 in the least significant position
must be 0. The carry output of the lower order
stage is connected to the carry input of the next
higher order stage.
 Hence this type of adder is called ripple-carry
adder.

PARALLEL ADDER
 In the least significant stage, A0, B0 and C0 (which is
0) are added resulting in sum S0 and carry C1. This
carry C1 becomes the carry input to the second stage.
 Similarly in the second stage, A1, B1 and C1 are
added resulting in sum S1 and carry C2, in the third
stage, A2, B2 and C2 are added resulting in sum S2
and carry C3, in the third stage, A3, B3 and C3 are
added resulting in sum S3 and C4, which is the output
carry.
 Thus the circuit results in a sum (S3 S2 S1 S0) and a
carry output (Cout).

PARALLEL ADDER
VERILOG HDL CODE - FULL ADDER (Gate-level)
// Module Name: FullAdder
module FullAdder(SUM, CARRY, A, B, Cin);
input A,B,Cin;
output SUM, CARRY;
wire W1,W2,W3,W4;
xor G1(W1,A,B);
xor G2(SUM,W1,Cin);
and G3(W2,A,Cin);
and G4(W3,B,Cin);
and G5(W4,A,B);
or G6(CARRY,W2,W3,W4);
endmodule
LOGIC DIAGRAM

PARALLEL ADDER
VERILOG HDL CODE - FULL ADDER (Gate-level)
module adder_4bit (S, Cout,A,B);
input [3:0] A ;
input [3:0] B ;
output [3:0]S ;
output Cout ;
wire [3:1]C;
FullAdder FA0(S[0],C[1],A[0],B[0],1'b0);
FullAdder FA1(S[1],C[2],A[1],B[1],C[1]);
FullAdder FA2(S[2],C[3],A[2],B[2],C[2]);
FullAdder
FA3(S[3],Cout,A[3],B[3],C[3]);
endmodule
LOGIC DIAGRAM

PARALLEL ADDER
VERILOG HDL CODE – 4-BIT PARALLEL ADDER (Test Bench)
module adder_4bit_tb;
reg [3:0] A;
reg [3:0] B;
wire [3:0] S;
wire Cout;
adder_4bit uut (.S(S), .Cout(Cout),
.A(A), .B(B));
initial begin
// Initialize Inputs
A = 5; B = 5; #100;
A = 15; B = 12; #100;
end
endmodule

Parallel Subtractor
Logic diagram of 4-bit parallel subtractor

Parallel Subtractor
Working of Parallel Subtractor
• The parallel binary subtractor is formed by combination of all full
adders with subtrahend complement input
• This operation considers that the addition of minuend along with
the 2’s complement of the subtrahend is equal to their
subtraction
• Firstly the 1’s complement of B is obtained by the NOT gate and 1
can be added through the carry to find out the 2’s complement
of B. This is further added to A to carry out the arithmetic
subtraction
• The process continues till the last full adder FAn uses the carry bit
Cn to add with its input An and 2’s complement of Bn to generate
the last bit of the output along last carry bit Cout

Parallel Adder/ Subtractor
Logic diagram of 4-bit parallel adder/ subtractor

Parallel Adder/ Subtractor
Working of Parallel Adder/ Subtractor
• The parallel binary adder/subtractor is formed by combination of all
full adders with a control input (M) to determine the operation.
• When M=0, the circuit performs 4-bit parallel addition; when M=1,
subtraction is performed.
• The XOR gates get input B and control input M.
• When M=0, number B is not complimented as shown below:
 Bi  0 = Bi . 1+ Bi’ . 0 = Bi
• When M=1, number B is complemented (2’s complement) as
indicated below:
 Bi  1 = Bi . 0 + Bi’ .1 = Bi’
• Hence, 4-bit parallel adder/ subtractor could be implemented using 4
FAs, 4 XOR gates and one control input.

Carry look-ahead Adder
• The addition of two binary numbers in parallel implies that all the
bits of the augend and addend are available for computation at
the same time.
• As in any combinational circuit, the signal must propagate
through the gates before the correct output sum is available in
the output terminals.
• The total propagation time is equal to the propagation delay of a
typical gate, times the number of gate levels in the circuit.
• The longest propagation delay time in an adder is the time it
takes the carry to propagate through the full adders.

• Since each bit of the sum output depends on the value of the
input carry, the value of Si at any given stage in the adder will be
in its steady-state final value only after the input carry to that
stage has been propagated.
• In this regard, consider output S3. Inputs A3 and B3 are available
as soon as input signals are applied to the adder.
• However, input carry C3 does not settle to its final value until C2
is available from the previous stage. Similarly, C2 has to wait for
C1 and so on down to C0.
• Thus, only after the carry propagates and ripples through all
stages will the last output S3 and carry C4 settle to their final
correct value.

• The number of gate levels for the carry propagation can be found from the circuit of the
full adder.
• The signals at Pi and Gi settle to their steady-state values after they propagate through
their respective gates. These two signals are common to all half adders and depend on
only the input augend and addend bits.
• The signal from the input carry Ci to the output carry Ci+1 propagates through an AND
gate and an OR gate, which constitute two gate levels.
• If there are four full adders in the adder, the output carry C4 would have 2 * 4 = 8 gate
levels from C0 to C4. For an n-bit adder, there are ‘2n’ gate levels for the carry to
propagate from input to output.

• The carry propagation time is an important attribute of the adder because it limits the
speed with which two numbers are added.
• Although the adder, or, for that matter, any combinational circuit—will always have
some value at its output terminals, the outputs will not be correct unless the signals are
given enough time to propagate through the gates connected from the inputs to the
outputs.
• Since all other arithmetic operations are implemented by successive additions, the time
consumed during the addition process is critical.
• An obvious solution for reducing the carry propagation delay time is to employ faster
gates with reduced delays. However, physical circuits have a limit to their capability.
• Another solution is to increase the complexity of the equipment in such a way that the
carry delay time is reduced. There are several techniques for reducing the carry
propagation time in a parallel adder.

• Consider the circuit of the full adder shown in Fig. If we define two new binary
variables,
• the output sum and carry can respectively be expressed as
• Gi is called a carry generate , and it produces a carry of 1 when both Ai and Bi are 1,
regardless of the input carry Ci.
• Pi is called a carry propagate , because it determines whether a carry into stage i will

• We now write the Boolean functions for the carry outputs of each stage and substitute
the value of each Ci from the previous equations:
• Since the Boolean function for each output carry is expressed in sum-of-products form,
each function can be implemented with one level of AND gates followed by an OR
gate.
• Note that this circuit can add in less time because C3 does not have to wait for C2 and
C1 to propagate; in fact, C3 is propagated at the same time as C1 and C2.
• This gain in speed of operation is achieved at the expense of additional complexity
(hardware).

• The three
Boolean
functions for C1,
C2, and C3 are
implemented in
the carry
lookahead
generator shown
in Fig.

BINARY MULTIPLIER
 Multiplication of binary numbers is performed in the
same way as in decimal numbers.
 The multiplicand is multiplied by each bit of the
multiplier starting from the least significant bit.
 Each such multiplication forms a partial product. Such
partial products are shifted one position to left.
 The final product is obtained from the sum of partial
products.

BINARY MULTIPLIER
 Consider the multiplication of two 2-bit numbers. The
multiplicand bits are B1 and B0, the multiplier bits are
A1 and A0, and the product is P3, P2, P1 and P0.
 The first partial product is formed by multiplying B0 by
A1A0. The multiplication of two bits such as A0 and B0
produces a 1 if both bits are 1; otherwise, it produces
a 0.
 This is identical to an AND operation. Therefore the
partial product can be implemented with AND gates
as shown in the diagram.
2-Bit by 2-Bit Multiplier

BINARY MULTIPLIER
 The second partial product is formed by
multiplying B1 by A1A0 and shifted one position to
the left. The two partial products are added with
two half adder (HA) circuits.

BINARY MULTIPLIER

BINARY MULTIPLIER
 Usually there are more bits in the partial products and
it is necessary to use full adders to produce the sum
of the partial products.
 The least significant bit of the product does not have
to go through an adder since it is formed by the
output of the first AND gate.
 A combinational circuit binary multiplier with more bits
can be constructed in a similar fashion. A bit of the
multiplier is ANDed with each bit of the multiplicand in
as many levels as there are bits in the multiplier.

BINARY MULTIPLIER
 The binary output in each level of AND gates are
added with the partial product of the previous
level to form a new partial product. The last level
produces the final product result.
 Consider a multiplier circuit that multiplies a
binary number of four bits by a number of four
bits.
 Let the multiplicand be represented by B3, B2, B1,
B0 and the multiplier by A3, A2, A1, and A0.

BINARY MULTIPLIER
 Since 4x4 multiplication process we need 16 AND
gates and three 4-bit parallel adders to produce a
product of eight bits.
 As shown in figure each shifted multiplicand
which is multiplied by either 0 or 1 depending on
the corresponding, multiplier bit is called partial
product.
 The final 8-bit product is obtained by adding all
partial products.

BINARY MULTIPLIER

BINARY MULTIPLIER
 The multiplication of B0 and A0 produces a 1 if both
bits are 1; otherwise it produces 0. This is identical to
AND gates operation. Therefore the partial products
can be implemented with AND gates.
 The 4-bit partial products are added using 4-bit
parallel adder. During addition of first partial product
three most significant bits of it are added to the
second partial product.
 As we take only three bits from the partial product,
the fourth bit (MSB) is considered as 0.

BINARY MULTIPLIER
 The three most significant bits and carry out of first
partial sum are then added to the third partial product.
 Finally the three most significant bits and carry out of
second partial sum are added to the fourth partial
product the carryout and third sum represents the five
most significant bits of the product.
 Least significant bits of first and second partial sum
represent P1 and P2 respectively & product B0A0
represents P0.

MAGNITUDE COMPARATOR
 A magnitude comparator is a combinational circuit that compares two
given numbers (A and B) and determines whether one is equal to,
less than or greater than the other.
 The output is in the form of three binary variables representing the
conditions A = B, A>B and A<B, if A and B are the two numbers
being compared.
Block diagram of magnitude comparator

Truth Table
Inputs Outputs
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
2-Bit Magnitude Comparator

K-Map Simplification

Logic Diagram

 Let us consider the two binary numbers A and B with
four digits each. Write the coefficient of the numbers
in descending order as,
A = A3A2A1A0
B = B3 B2 B1 B0
 Each subscripted letter represents one of the digits in
the number. It is observed from the bit contents of two
numbers that A = B when A3 = B3, A2 = B2, A1 = B1
and A0 = B0.

 When the numbers are binary they possess the value
of either 1 or 0, the equality relation of each pair can
be expressed logically by the equivalence function as
Xi = Ai Bi + Ai ′ Bi ′ for i = 0, 1, 2, 3
Or, Xi = (A  B)′ Or, Xi ′ = A  B
Or, Xi = (Ai Bi ′ + Ai ′Bi )′
where, Xi =1 only if the pair of bits in position i are
equal (i.e., if both are 1 or both are 0).

 To satisfy the equality condition of two numbers A and
B, it is necessary that all Xi must be equal to logic 1.
This indicates the AND operation of all Xi variables.
 In other words, we can write the Boolean expression
for two equal 4-bit numbers.
(A = B) = X3X2X1 X0. (where X = A xnor B)
 The binary variable (A=B) is equal to 1 only if all pairs
of digits of the two numbers are equal.

 To determine if A is greater than or less than B, we
inspect the relative magnitudes of pairs of significant
bits starting from the most significant bit.
 If the two digits of the most significant position are
equal, the next significant pair of digits is compared.
The comparison process is continued until a pair of
unequal digits is found.
 It may be concluded that A>B, if the corresponding
digit of A is 1 and B is 0. If the corresponding digit of A
is 0 and B is 1, we conclude that A<B.

 In a 4-bit comparator the condition of A>B can be possible in the
following four cases:
1. If A3 = 1 and B3 = 0
2. If A3 = B3 and A2 = 1 and B2 = 0
3. If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0
4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and B0 = 0
 Similarly the condition for A<B can be possible in the following four
cases:
1. If A3 = 0 and B3 = 1
2. If A3 = B3 and A2 = 0 and B2 = 1
3. If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1
4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and B0 = 1

 Therefore, we can derive the logical expression of such
sequential comparison by,
(A>B) = A3B3′ +X3A2B2′ +X3X2A1B1′ +X3X2X1A0B0′
(A<B) = A3′B3 +X3A2′B2 +X3X2A1′B1 +X3X2X1A0′B0
 The symbols (A>B) and (A<B) are binary output variables that
are equal to 1 when A>B or A<B, respectively.
 The gate implementation of the three output variables just
derived is simpler than it seems because it involves a certain
amount of repetition.
 The unequal outputs can use the same gates that are needed
to generate the equal output.

Block diagram of 4-Bit magnitude comparator (IC7485)

Logic diagram of 4-Bit
magnitude comparator

Block diagram of 8-Bit
magnitude comparator

 Comparators are used in central processing units
(CPUs) and microcontrollers (ALU).
 These are used in control applications in which the
binary numbers representing physical variables such
as temperature, position, etc. are compared with a
reference value.
 Comparators are also used as process controllers
and for Servo motor control.
 Analogue-to-Digital converters, (ADC)
Applications of Magnitude Comparator

Parallel Adder_Mul_Mag.pptx

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