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13.703 Embedded Systems
Prepared By: Mahesh S
Assist. Professor
MZIST, Chengannur
Page 1
16F873 PIC Microcontroller
MODULE IV

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MZIST, Chengannur
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ARCHITECTURAL FEATURES OF 16F873 PIC MICRO CONTROLLER
2.1 ARCHITECTURE OF PIC 16F873 MICROCONTROLLER
The internal logic design of a device is called its architecture. The Microcontroller architecture determines
how and what various operations are performed. The architecture of the PIC 16F873 Microcontroller is shown
in Figure 2.1.
Figure 2.1 Block Diagram of PIC 16F873 Microcontroller

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The architectural features of PIC 16F873 Microcontroller are given below
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program branches, which are two cycle
• Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle
• Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8 bytes of Data Memory
(RAM), Up to 256 x 8 bytes of EEPROM data memory
• Pinout compatible to the PIC 16C73B/74B/76/77
• Interrupt capability (up'to 14 sources)
• Eight level deep hardware stack
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS FLASH/EEPROM technology
• Fully static design
• In-Circuit Serial Programming a (ICSP) via two pins
• Single 5V In-Circuit Serial Programming capability
• In-Circuit Debugging via two pins
• Processor read/write access to program memory
• Wide operating voltage range: 2.0V to 5.5V
• High Sink/Source Current: 25 mA
• Commercial and Industrial temperature ranges
• Low-power consumption:
- < 2 mA typical @ 5V, 4 MHz
- 20 mA typical @ 3V, 32 kHz -< 1 mA typical standby current
❖ Peripheral Features
• TimerO: 8-bit timer/counter with 8-bit prescaler

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• Timer 1: 16-bit timer/counter with prescaler can be incremented during sleep Via
external crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period register, prescaler
and postscaler
• Two Capture, Compare, PWM modules
- Capture is 16-bit, max. Resolution is 12.5 ns
- Compare is 16-bit, max. Resolution is 200 ns
- PWM max. Resolution is 10-bit
• 10-bit multi-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with SPIa (Master Mode) and I2Ca (Master/Slave)
• Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection
Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls
❖ PIC 16F873 Microcontroller Pin Configuration
The PIC 16F873 Microcontroller is a 28 pin DIP. The Pin diagram
contains the abbreviated names of the signals for each pin. It is important to note that many of the pins are
used for more than one function. Programming functions or physical pin connections determine the use of any
multifunction pins. The system designer decides which of these functions is to be used and designs the
hardware and software affecting that pin accordingly.
Figure 2.2 Pin Diagram of PIC 16F873 Microcontroller

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2.3 MEMORY ORGANIZATION
There are three memory blocks in PIC 16F873 Microcontroller [13]. The Program Memory and Data Memory
have separate buses so that concurrent access can occur.
2.3.1 Program Memory Organization
The PIC16F87X devices have a 13-bit program counter capable of addressing an 8K x 14 program memory
space. The PIC 16F873 device has 4K x 14 words of FLASH program memory. Accessing a location above
the physically implemented address will cause a wraparound. The reset vector is at OOOOh and the interrupt
vector is at 0004h.
The PIC 16F873 Program memory Map and stack is shown in Figure 2.3.
Figure 2.3 PIC16F873 Program Memory Map And Stack

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2.3.2 Data Memory Organization
The data memory is partitioned into multiple banks, which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>) and RPO (STATUS<5>) are the bank select bits. These
bits are represented in the Table 2.2.
Table 2.2 Bank Select Bits
Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special
Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as
Static RAM. All implemented banks contain Special Function Registers. Some “high use” Special Function
Registers from one bank may be mirrored in another.
2.3.3 Special Function Registers
Special Function Registers [14] are special elements of RAM, their purpose predefined by the manufacturer.
Each of these registers is named and controls a certain subsystem of MCU. For example: by writing zeros and
ones to the SFR register which controls an I/O port, each of these pins can be designated as input or output
(each register bit corresponds to one of the port pins).
The Special Function Registers are registers used by the CPU and peripheral modules for controlling the
desired operation of the device. These registers are implemented as static RAM. The Special Function
Registers can be classified into two sets; core (CPU) and peripheral.
Status Register
The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for
data memory. The STATUS register can be the destination for any instruction, as with any other register. If
the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to
these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO
and PD bits are not writable, therefore, the result of an instruction with the STATUS register as destination

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may be different than intended. It is recommended, that only BCF, BSF, SWAPF and MOVWF instructions
are used to alter the STATUS register, because these instructions do not affect the Z, C or DC bits from the
STATUS register.
❖ OptionReg Register
The OPTION_REG Register is a readable and writable register, which contains various control bits to
configure the TMRO presealer/WDT postscaler (single assignable register known also as the prescaler), the
External INT Interrupt, TMRO and the weak pull-ups on PORTB.
❖ PIE1 Register
The PIE1 register contains the individual enable bits for the peripheral interrupts.
❖ PIR1 Register
The PIR1 register contains the individual flag bits for the peripheral interrupts.
❖ PIE2 Register
The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt, the SSP bus collision
interrupt, and the EEPROM write operation interrupt.
❖ PIR2 Register
The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP bus collision interrupt and the
EEPROM write operation interrupt.
❖ PCON Register
The Power Control (PCON) Register contains flag bits to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watch-dog Reset (WDT) and an external MCLR Reset.
2.4 I/O PORTS
Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.
There are three ports in PIC 16F873 Microcontroller. They are Port A, Port B and Port C.

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□ PORTA and the TRISA Register
PORTA is a 6-bit wide bi-directional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in
a hi-impedance mode). Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output.
□ PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in
a hi-impedance mode). Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output.
□ PORTC and the TRISC Register
r
PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a
TRISC bit (=1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in
a hi-impedance mode). Clearing a TRISC bit (=0) will make the corresponding PORTC pin an output.
PORTC pins have Schmitt Trigger input buffers.
2.5 TIMERS
Majority of programs utilizes these miniature electronic "stopwatches". Commonly, timers are 8 or 16-bit
registers whose value automatically increases upon an impulse. If timer is stimulated by an internal MCU
oscillator, it can be used for measuring time between two occurrences (register value at the start of measuring
= Tl, register value at the end of measuring = T2, elapsed time = T2-Tl). If timer is triggered by impulses
from an external source, instrument behaves like a counter. In both cases, filling the register resets the counter
and the occurrence is recorded in a particular bit of SFR register (Overflow flag). This makes possible to
measure longer time periods. Also, if enabled, this flag can cause an interrupt for breaking the program and
carrying out a designated routine.
2.5.1 Timer 0 Module
The Timer0 module timer/counter has the following features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler

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• Internal or external clock select
• Interrupt on overflow from FFh to OOh
• Edge select for external clock
Timer mode is selected by clearing bit TOCS (OPTION REG<5>). In timer mode, the TimerO module will
increment every instruction cycle (without prescaler). If the TMRO register is written, the increment is
inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value
to the TMRO register. Counter mode is selected by setting bit TOCS (OPTION REG<5>). In counter mode,
TimerO will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is
determined by the TimerO Source Edge Select bit TOSE (OPTION_REG<4>). Clearing bit TOSE selects the
rising edge. The prescaler is mutually exclusively shared between the TimerO module and the watchdog
timer. The prescaler is not readable or writable
2.5.2 Timer1 Module
The Timerl module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L), which
are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from OOOOh to FFFFh
and rolls over to OOOOh. The TMR1 Interrupt, if enabled, is generated on overflow, which is latched in
interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1
interrupt enable bit TMR1IE (PIE1<0>). Timerl can operate in one of two modes:
• As a timer
* As a counter
The operating mode is determined by the clock select bit, TMR1CS (T1C0N<1>). In timer mode, Timer 1
increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock
input. Timer 1 can be enabled/disabled by setting/clearing control bit TMRION (T1CON<0>). Timer 1 also
has an internal “reset input”. This reset can be generated by either of the two CCP modules counter mode is
selected by setting bit TMR1CS. In this mode, the timer increments on every rising edge of clock input on pin
RC1/T10SI/CCP2, when bit T10SCEN is set, or on pin RCO/TIOSO/TICKI, when bit T10SCEN is cleared.
Timerl may operate in asynchronous or synchronous mode depending on the setting of the TMR1CS bit.
2.6 ADDRESSABLE UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Communications Interface or SCI). The USART [15] can be

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configured as a full duplex asynchronous system that can communicate with peripheral devices such as CRT
terminals and personal computers, or it can be configured as a half duplex synchronous system that can
communicate with peripheral devices such as A/D or D/A integrated circuits, serial EEPROMs etc.
The USART can be configured in the following modes:
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be set in order to configure pins RC6/TX/CK and
RC7/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter. The USART module also
has a multi- processor communication capability using 9-bit address detection.
 USART Asynchronous Mode
In this mode, the USART uses standard non-retum-tozero (NRZ) format (one start bit, eight or nine data bits,
and one stop bit). The most common data format is 8 bits. An on-chip, dedicated, 8-bit baud rate generator
can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives
the LSB first. The USART’s transmitter and receiver are functionally independent, but use the same data
format and baud rate. The baud rate generator produces a clock either xl6 or x64 of the bit shift rate,
depending on bit BRGH (TXSTA<2>). Parity is not supported by the hardware, but can be implemented in
software (and stored as the ninth data bit). Asynchronous mode is stopped during SLEEP. Asynchronous
mode is selected by clearing bit SYNC (TXSTA<4>).
The USART Asynchronous module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
 USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in Figure 2.4. The heart of the transmitter is to transmit
(serial) shift register (TSR). The shift register obtains its data from the read/write transmit buffer, TXREG.
The TXREG register is loaded with data in software. The TSR register is not loaded until the STOP bit has
been transmitted from the previous load. As soon as the STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and flag bit TXIF (PIR1<4>) is set. This interrupt can be

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enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT
(TXSTA<1>) shows the status of the TSR register. Status bit TRMT is a read only bit, which is set when the
TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine
if the TSR register is empty. Transmission is enabled by setting enable bit TXEN (TXSTA<5>).
Figure 2-4 USART Transmit Block Diagram
Steps to follow when setting up an Asynchronous Transmission:
• Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired,
set bit BRGH.
• Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN.
• If interrupts are desired, then get enable bit TXIE.
• If 9-bit transmission is desired, then set transmit bit TX9.
• Enable the transmission by setting bit TXEN, which will also set bit TXIF.
• If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D.
• Load data to the TXREG register (starts transmission).
 USART ASYNCHRONOUS RECEIVER
The receiver block diagram is shown in Figure 2.5.The data is received on the RC7/RX/DT pin and drives the
data recovery block. The data recovery block is actually a high speed shifter operating at xl6 times the baud
rate, whereas the main receive serial shifter operates at the bit rate or at FOSC.Once asynchronous mode is

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selected, reception is enabled by setting bit CREN (RCSTA<4>). The heart of the receiver is to receive
(serial) shift register (RSR). After sampling the STOP bit, the received data in the RSR is transferred to the
RCREG register (if it is empty). If the transfer is complete, flag bit RCIF (PIR1<5>) is set. The actual
interrupt can be enabled/disabled by setting/clearing enable bit RCIE (PIEl<5>).Flag bit RCIF is a read only
bit which is cleared by the hardware. It is cleared when the RCREG register has been read and is empty. The
RCREG is a double buffered register (i.e. it is a two deep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the
detection of the STOP bit of the third byte, if the RCREG register is still full, the overrun error bit OERR
(RCSTA<1>) will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve
the two bytes in the FIFO. Overrun bit OERR has to be cleared in software. This is done by resetting the
receive logic (CREN is cleared and then set). If bit OERR is set, transfers from the RSR register to the
RCREG register are inhibited, so it is essential to clear error bit OERR if it is set. Framing error bit FERR
(RCSTA<2>) is set if a stop bit is detected as clear. Bit FERR and the 9th receive bit are buffered the same
way as the receive data. Reading the RCREG will load bits RX9D and FERR with new values, therefore it is
essential for the user to read the RCSTA register before reading RCREG register in order not to lose the old
FERR and RX9D information.
Figure 2-5 USART Receiver Block Diagram
Steps to follow when setting up an Asynchronous Reception:
• Initialize the SPBRG register for the appropriate baud rate. If a high- speed baud rate is desired, set bit
BRGH.
• Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN.

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• If interrupts are desired, then set enable bit RCIE.
• If 9-bit reception is desired, then set bit RX9.
• Enable the reception by setting bit CREN.
• Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit
RCIE is set.
• Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during
reception.
• Read the 8-bit received data by reading the RCREG register.
• If any error occurred, clear the error by clearing enable bit CREN.
2.7 ANALOG TO DIGITAL CONVERTER
The Analog-to-Digital (A/D) Converter module has five inputs for the 28-pin devices and eight for the other devices.
The analog input charges a sample and hold capacitor. The output of the sample and hold capacitor is the input into the
converter. The converter then generates a digital result of this analog level via successive approximation. The A/D
conversion of the analog input signal results in a corresponding 10-bit digital number. The A/D module has
high and low voltage reference input that is software selectable to some combination of VDD, VSS, RA2 or
RA3.The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To
operate in sleep, the A/D clock must be derived from the A/D’s internal RC oscillator.
The A/D module has four registers. These registers are;
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control RegisterO (ADCONO)
• A/D Control Registerl (ADCON1)
The ADCONO register controls the operation of the A/D module. The ADCON1 register configures the
functions of the port pins. The port pins can be configured as analog inputs (RA3 can also be the voltage
reference) or as digital I/O.The ADRESH: ADRESL registers contain the 10-bit result of the A/D conversion.
When the A/D conversion is complete, the result is loaded into this A/D result register pair, the GO/DONE bit
(ADCONO<2>) is cleared and the A/D interrupt flag bit ADIF is set. The block diagram of the A/D module
is shown in Figure 2.6.After the A/D module has been configured as desired, the selected channel must be
acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits
selected as inputs.
The following steps should be followed for doing an A/D conversion:

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> Configure the A/D module:
• Configure analog pins / voltage reference /and digital I/O (ADCON1)
• Select A/D input channel (ADCONO)
• Select A/D conversion clock (ADCONO)
• Turn on A/D module (ADCONO)
> Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
> Wait the required acquisition time.
> Start conversion:
• Set GO/DONE bit (ADCONO)
> Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
> Read A/D Result register pair (ADRESH: ADRESL), clear bit ADIF if required.
> For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is required before next acquisition starts.
>
Figure 2-6 A/D Block Diagram

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2.8. WATCH DOG TIMER
The Watchdog Timer is as a free running on-chip RC oscillator which does not require any external
components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that
the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been
stopped. The block diagram is shown in Figure 2.7.
During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device
is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation
(Watchdog Timer Wake-up). The TO bit in the STATUS register will be cleared upon a Watchdog Timer
time-out. The WDT can be permanently disabled by clearing configuration bit WDTE. Values for the WDT
prescaler may be assigned using the OPTION REG register.
Figure 2.7 WATCHDOG TIMER BLOCK DIAGRAM

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