Pipeline processing - Computer Architecture
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This document discusses instruction pipelining in processors. It begins with an introduction that defines pipelining as breaking down operations into sequential stages that can overlap execution. An example is given of pipelining laundry tasks to complete work more efficiently. The document then explains how instruction execution in computers lends itself to pipelining by separating tasks like fetch, decode, and execute into distinct stages. A six-stage instruction pipeline and timing diagram are presented. Advantages of pipelining include more efficient use of resources and faster execution for large programs. However, pipeline hazards like structural, data, and control hazards can cause problems if not addressed properly.
![PIPELINE CASE – [NON PIPELINED
LAUNDRY]
Takes a total of 6 hours in above case](https://image.slidesharecdn.com/pipelineprocessing-170111095909/85/Pipeline-processing-Computer-Architecture-6-320.jpg)
![PIPELINE CASE – [PIPELINED LAUNDRY]
Using this
method, the
laundry
would be
done at 9:30.](https://image.slidesharecdn.com/pipelineprocessing-170111095909/85/Pipeline-processing-Computer-Architecture-7-320.jpg)
Pipeline processing - Computer Architecture
- 1. PIPELINE PROCESSING Created & Presented by: S. Hasnain Raza PIMSAT - Pakistan
- 2. AGENDA ▪ Introduction ▪ Pipeline Case – Non pipelined Vs Pipeline ▪ Pipeline processors ▪ Instruction Pipeline ▪ Timing Diagram for Instruction Pipeline Operation ▪ Pipeline Advantages ▪ Can Pipelining Get Us Into Trouble?
- 3. INTRODUCTION ▪ A Pipelining is a series of stages, where some work is done at each stage in parallel. ▪ The stages are connected one to the next to form a pipe - instructions enter at one end, progress through the stages, and exit at the other end. ▪ A pipeline is a set of data processing elements connected in series, where the output of one element is the input of the next one. (Wikipedia)
- 4. INTRODUCTION (CONT..) ▪ Pipelining is an speed up technique where multiple instructions are overlapped in execution on a processor. ▪ The elements of a pipeline are often executed in parallel or in time- sliced fashion; in that case, some amount of buffer storage is often inserted between elements. ▪ Buffer or data buffer: ▪ It is a region of a physical memory storage used to temporarily store data while it is being moved from one place to another.
- 5. PIPELINE CASE – LAUNDRY ▪ 4 loads of laundry that need to washed, dried, and folded. ▪ 30 minutes to wash ▪ 40 minutes to dry ▪ and 20 min. to fold. ▪ We have 1 washer, 1 dryer, and 1 folding station. ▪ What’s the most efficient way to get the 4 loads of laundry done?
- 6. PIPELINE CASE – [NON PIPELINED LAUNDRY] Takes a total of 6 hours in above case
- 7. PIPELINE CASE – [PIPELINED LAUNDRY] Using this method, the laundry would be done at 9:30.
- 8. PIPELINE PROCESSORS ▪ Computers, like laundry, typically perform the exact same steps for every instruction: ▪ Fetch an instruction from memory ▪ Decode the instruction ▪ Execute the instruction ▪ Read memory to get input ▪ Write the result back to memory
- 9. INSTRUCTION PIPELINE ▪ Instruction execution process lends itself naturally to pipelining ▪ overlap the subtasks of instruction fetch, decode and execute ▪ Instruction pipeline has six operations ▪ Fetch instruction (FI) ▪ Decode instruction (DI) ▪ Calculate operands (CO) ▪ Fetch operands (FO) ▪ Execute instructions (EI) ▪ Write result (WR)
- 10. INSTRUCTION PIPELINE (CONT..) ▪ Operation Briefly Explained ▪ Fetch instruction (FI) ▪ The IF stage is responsible for obtaining the requested instruction from memory. The instruction and the program counter are stored in the register as temporary storage ▪ Decode instruction (DI) ▪ The DI stage is responsible for decoding the instruction and sending out the various control lines to the other parts of the processor. ▪ Calculate operands (CO) ▪ The CO stage is where any calculations are performed. The main component in this stage is the ALU. The ALU is made up of arithmetic, logic and capabilities. ▪ Fetch operands (FO) & Execute instructions (EI) ▪ The FO and EI stages are responsible for storing and loading values to and from memory. They are also responsible for input and output from the processor respectively. ▪ Write result (WR) ▪ The WO stage is responsible for writing the result of a calculation, memory access or input into the register file.
- 11. TIMING DIAGRAM FOR INSTRUCTION PIPELINE OPERATION
- 12. ADVANTAGES ▪ Pipelining makes efficient use of resources. ▪ Quicker time of execution of large number of instructions ▪ The parallelism is invisible to the programmer.
- 13. CAN PIPELINING GET US INTO TROUBLE? “YES” ▪ Pipeline Hazards ▪ Structural hazards ▪ Attempt to use the same resource by two different instructions at the same time. ▪ Data hazards ▪ Attempt to use data before it is ready ▪ Control hazards ▪ Attempt to make a decision about program control flow before the condition has been evaluated and the new PC target address calculated
- 14. THANK YOU! Pipeline Processing Advance Computer Architecture S. Hasnain Raza PIMSAT - Pakistan