Power estimation in low power vlsi design
- 1. Power Estimation Naehyuck Chang Dept. of EECS/CSE Seoul National University [email protected] 1
- 2. ELPLEmbedded Low-Power Laboratory Contents SPICE power analysis Power estimation basics Signal probability calculation Switching Activity Leakage Estimation 2
- 3. Embedded Low-Power Laboratory Circuit-level power analysis SPICE is the de facto standard power analysis tool Simulation program with integrated circuit emphasis A lot of SPICE related literatures and simulators HSPICE, PSPICE, and so on The reference for the higher abstraction levels Accurate but slow Analytical models of MOSFET Recently, faster analysis tools were introduced E.g. PowerMill, Spectre, and so on Still accuracy is inferior to SPICE 3
- 4. Embedded Low-Power Laboratory SPICE basics Solving a large matrix of nodal current using Krichoff’s Current Law (KCL) Primitive elements Registers, capacitors, inductors, current sources, and voltage sources More complex elements Such as diodes and transistors Constructed from the primitive elements Analysis modes DC analysis Transient analysis 4
- 5. Embedded Low-Power Laboratory SPICE power analysis Can estimate all types of power consumption Dynamic/static/leakage Not feasible for the entire chip due to the computation complexity Can be used as a characterization tool for higher abstraction level analysis Can consider process and other parameter’s variation BEST/TYPICAL/WORST 5
- 6. Embedded Low-Power Laboratory Discrete transistor modeling/analysis To speed up the analysis Lose accuracy Typical methods Circuit model Approximate the complex equations into a linear equation Tabular transistor model Express the transistor models in tabular forms Switch model Consider a transistors as a two-state switch (on/off) 6
- 7. Embedded Low-Power Laboratory Circuit model • The linear equation should be numerically evaluated whenever the operating points change 7
- 8. Embedded Low-Power Laboratory Pre-compute a current table Look up the table instead of solving an equation Table format One-time characterization effort for each MOS Event-driven appraoch can be used for speed-up Nearly two orders of magnitude improvement (speed, size) Tabular transistor model Vgso Vdso ids 0.1 0.1 1 … … … 5 5 10 8
- 9. Embedded Low-Power Laboratory Switch model • Further speed-up, but less accuracy • RC calculation for timing • Power is estimated from the switching frequency and capacitance 9
- 10. Embedded Low-Power Laboratory Power characterization for cell library Circuit-level power analysis is time consuming Need to speed up with reasonable accuracy loss Levels beyond gate level will be discussed later Partially similar to delay characterization Dynamic power Capacitive power dissipation Internal switching power dissipation Leakage power Accuracy depends on the model of circuit simulation Iterative analytic estimation Simulation based approach 10
- 11. Embedded Low-Power Laboratory Power characterization flow Accuracy vs. speed Too many input patterns too many simulation runs Too many input patterns probabilistic analysis 010110 110111 000100 ……… Circuit Simulator A large # of current waveforms Average Power Average Probability Values Analysis tools Power 11
- 12. Embedded Low-Power Laboratory Simulation-based cell characterization Parameters Input pattern (logical value) Input slope Output loading capacitance Process condition Total # of runs of simulation is the multiplication of the possible number of values of each parameter Some parameters are continuous Input slope, output loading capacitance Piece-wise linear approximation is widely used Process/operation condition BEST/TYPICAL/WORST 12
- 13. Embedded Low-Power Laboratory Example: 2-input NAND (I) Possible input patterns Dynamic power A B C Power 1 r f ? 1 f r ? r 1 f ? f 1 r ? A B C Power 0 0 1 ? 0 1 1 ? 1 0 1 ? 1 1 0 ? Static power 8 simulation runs! 13
- 14. Embedded Low-Power Laboratory Input slope Depending on the predecessor Capacitance Depending on the successor proportional to the # of fan-outs If we consider four points for capacitance Total # of simulation runs for a single input 2 (rise / fall) x 4 (# of input slopes) x 4 (# of capacitance points) = 32 points Example: 2-input NAND (II) 14
- 15. Embedded Low-Power Laboratory Example: 2-input NAND (III) Process/operation condition Temperature Process variations such as doping density Typically use 3 conditions are widely used Total # of simulations For dynamic power (2 x 2) x S x C x P For static power 22 x P 15
- 16. Embedded Low-Power Laboratory Additional factors to be characterized Output slope Used as an input slope of the successor Need to know for each simulation point Input capacitance Used for computing the total output capacitance of the predecessor Can be estimated by the area of gate (W/L) and Tox Parasitics: Cgs/Cgd All the information should be included in the library 16
- 17. Embedded Low-Power Laboratory Tool flow input pattern generator Circuit simulator Simulation Analyzer Library generator Library information Circuit netlist Slope/Cap information Synthesis library Simulation library 17
- 18. Embedded Low-Power Laboratory Pre-requisite to move to module 8 If we ignore internal capacitance of a logic gate Parameters C: switched capacitance f : the frequency of operation For aperiodic signals: the average # of signal transitions per unit time Called signal activity Our concern How to estimate f in a probabilistic manner Probability-based power estimation 18
- 19. Embedded Low-Power Laboratory Modeling of signals To model the digital signals, need to know Signal probability Signal activity g(t), t ∈(-∞, ∞) A stochastic process that takes the values of logical 0 or 1 Transitioning from one to the other at random times SSS: Strict-Sense Stationary Mean ergodic Constant mean with a finite variance g(t) and g(t+τ) become uncorrelated as τ ∞ 19
- 20. Embedded Low-Power Laboratory Signal probability P(g=1) : signal probability Signal activity ng(t): # of transitions of g(t) in the time interval between –T/2 and +T/2 Signal probability and activity 20 P(g) = lim T→∞ 1 2T Z +T −T g(t)dt A(g) = lim T→∞ ng(T) T
- 21. Embedded Low-Power Laboratory Signal probabilities of simple gates Inverter AND gate OR gate 21 Assumption g1, g2, …, gn are independent Output signal probability Determined by the given boolean function NOT: 1 – AND: multiply OR NOT ((NOT) AND (NOT))
- 22. Embedded Low-Power Laboratory Signal probability calculation (I) By Parker and McClusky Algorithm: Compute signal probabilities Input: Signal probabilities of all the inputs to the circuit Output: Signal probabilities of all nodes of the circuit Stpe1: For each input signal and gate output in the circuit, assign a unique variable Step2: Starting at the inputs and proceeding to the outputs, write the expression for the output of each gate as a function (using standard expressions for each gate type for probability of its output signal in terms of its mutually independent primary input signals) Step3: Suppress all exponents in a given expression to obtain the correct probability for that signal 22
- 23. Embedded Low-Power Laboratory Signal probability calculation (II) Step 3 for protecting recovergent fanout W/o step 3, the reconvergent fanout node may have a signal probability higher than 1 A boolean function f n: # of independent inputs p: # of products αi: some integer Called as the sum of probability products of f 23
- 24. Embedded Low-Power Laboratory Signal probability calculation: Example y = x1x2 + x1x3, xi, I = 1, 2, 3 are mutually independent z = x1x2’ + y P(y) = P(x1x2) + P(x1x3) – P(x1x2)P(x1x3) = P(x1)P(x2) + P(x1)P(x3) – P(x1)P(x2)P(x3) P(z) = P(x1x2’) + P(y) – P(x1x2’)P(y) = P(x1)P’(x2) + P(x1)P(x2) + P(x1)P(x3) – P(x1)P(x2)p(x3) – P(x1)P’(x2)(P(x1)P(x2) + P(x1)P(x3) – P(x1)P(x2)P(x3)) P(x2)P’(x2) = P(x2)(1 – P(x2)) = 0 P(z) = P(x1)P’(x2) + P(x1)P(x2) + P(x1)P(x3) – P(x1)P(x2)p(x3) – P(x1)P’(x2)P(x3) 24
- 25. Embedded Low-Power Laboratory BDD: Binary Decision Diagram Shannon’s expansion Cofactors w.r.t. xi and x’i Example f = ab + c Signal probability using BDD (I) a b c 0 1 25
- 26. Embedded Low-Power Laboratory Signal probability using BDD (II) P(f) A depth first traversal of BDD, with a post order evaluation of P(.) at every node is required for evaluation of P(f) 26
- 27. Embedded Low-Power Laboratory References http://public.itrs.net Gary K. Yeap, “Practical Low Power Digital VLSI Design”, Kluwer Academic Publishers, 1997 Kaushick Roy and Sharat C. Prasad, “Low Power CMOS VLSI: Circuit Design”, Wiley Interscience, 2000 Kiat-Seng Yeo, Kaushik Roy, “Low Voltage, Low Power VLSI Subsystems”, McGraw-Hill, 2004 27
- 28. ELPLEmbedded Low-Power Laboratory 28 Switching Activity Activity Factor: System clock frequency = f Let fsw = αf, where α = activity factor If the signal is a clock, α = 1 If the signal switches once per cycle, α = ½ Dynamic gates: switch either 0 or 2 times per cycle, α = ½ Static gates: depending on design, but typically α = 0.1 Switching power:
- 29. ELPLEmbedded Low-Power Laboratory 29 Switching Activity Abnormal switching activity Glitch power Power dissipated in intermediate transitions during the evaluation of the logic function Unbalanced delay paths are principle cause Usually 8% -25% of dynamic power
- 30. ELPLEmbedded Low-Power Laboratory 30 Switching Activity Transition Probability Dynamic power is data dependent Activity factor is dependent on the run-time data Switching activity, P0→1, has two components A static component: function of the logic topology A dynamic component: function of the timing behavior (glitch) Static transition probability P0→1 = Pout=0 Pout=1= P0(1-P0) With input signal probabilities PA=1=1/2 and PB=1=1/2 NOR static transition probability = 3/4 x 1/4 = 3/16 2-input NOR Gate
- 31. ELPLEmbedded Low-Power Laboratory 31 Switching Activity Transition Probability Switching activity is a strong function of the input signal statistics Generalized switching activity of a 2 input NOR gate P0→1 = P0P1= (1-(1-PA)(1-PB)) (1-PA)(1-PB) Transition probability for basic gates Transition probability for 2 input NOR gates
- 32. ELPLEmbedded Low-Power Laboratory 32 Switching Activity Transition Probability Transition probability propagation C: P0→1 = P0P1= (1-PA) PA =1/2 x 1/2 = 1/4 D: P0→1 = P0P1= (1-PCPB) PCPB = (1 –(1/2 x 1/2)) x (1/2 x 1/2) = 3/16
- 33. ELPLEmbedded Low-Power Laboratory 33 Switching Activity Signal Probability (advanced) Generalized switching activity in combinational logic Boolean difference: Switching activity in sequential logic Estimation of glitch power
- 34. ELPLEmbedded Low-Power Laboratory 34 Switching Activity Decreasing the switching activities No or little performance and/or functional degradation Different coding techniques Fewer bit transitions between two states Boolean expressions simplification Gate minimization Avoid glitches Get rid off unnecessary transitions Power down modes Turn off parts of that are not in use
- 35. ELPLEmbedded Low-Power Laboratory 35 Switching Activity Decreasing the switching activities Example: gray coding Hamming distance of one Used when a sequence is predictable FSMs Address busses Makes full use of the bit-width 000 100 101 111 110 001 011 010
- 36. ELPLEmbedded Low-Power Laboratory 36 Leakage Estimation Transistor leakage estimation Leakage power components Subthreshold leakage is the focus in leakage current modeling (DIBL)
- 37. ELPLEmbedded Low-Power Laboratory 37 Leakage Estimation Transistors in a circuit Leakage current is strongly dependent on the relative position of on and off devices in a transistor network Position of devices If transistors are connected in parallel and turned off, VDS and VS are similar for each other Leakage current can be calculated independently and summed up If transistors are connected in series and turned off Subthreshold current though each transistor must be the same Voltage of the I-th transistor
- 38. ELPLEmbedded Low-Power Laboratory 38 Leakage Estimation Large-circuit leakage current computation Stack-based leakage estimation On transistors are considered as a short circuit Ignorance of the on resistance of transistors The leakage current of a transistor in parallel with an on transistor is ignored VDS is estimated for the remaining transistors using Leakage power
- 39. ELPLEmbedded Low-Power Laboratory 39 Leakage Estimation Very large-circuit leakage estimation Probabilistic approach Huddles of large-circuit leakage current calculation Calculation of the leakage current is complicated due to highly nonlinear behavior of the drain current wrt source/drain voltage SPICE simulation by using nonlinear model is still very expensive Not feasible for the repeated evaluation of large circuits Leakage current of a circuit is highly dependent on the circuit state State probability must be considered
- 40. ELPLEmbedded Low-Power Laboratory 40 Leakage Estimation State probability Three-input NAND SPICE leakage simulation
- 41. ELPLEmbedded Low-Power Laboratory 41 Leakage Estimation Gate state estimation Necessary to simulate a substantial portion of the gates’ states to obtain accurate average leakage of each gate Requires extremely large number of random global circuit vectors Complexity reduction method Probabilistic approach eliminates the need to do simulation over all 2n A small subset of all the possible states is evaluated, based on the notion of dominant-leakage states
- 42. ELPLEmbedded Low-Power Laboratory 42 Leakage Estimation Calculation of state probability Statistical simulation to measure the average leakage of an entire circuit Monte Carlo experiments In each iteration, a randomly chosen circuit state is applied Probabilistic approach is more effective than statistical simulation for optimization purpose Leakage optimization relies on accurate estimation rather than the estimation of the total leakage
- 43. ELPLEmbedded Low-Power Laboratory 43 Leakage Estimation Further simplification of the leakage calculation Dominant leakage states Leakage current in some states is significantly smaller than other states A state with more than one off transistor in a path from VDD to GND results in far less leakage than a state with one off transistor (dominant leakage state) A set of dominant leakage states is generally small Example: three-input NAND gate SPICE simulation Average leakage is 1.78925 nA Set of dominant leakage D={011, 101, 110, 111} Only consideration of D, the average leakage is 1.7055 nA with 4.68% error