PPT on 8085 Microprocessor
- 2. CONTENT Introduction of 8085 Pin Diagram of 8085 Pin Description of 8085 Architecture of 8085 Description of the Architecture Timing and state diagram Memory interfacing of 8085 Microprocessor Memory mapping of 8085 Microprocessor Example 8085 Memory Interfacing Interfacing IO devices with 8085 8085 Interrupts 8085 Interrupts types Responding to In t e r r u p t s 8085 Program example Demultiplexing AD7-AD0
- 3. Introduction of 8085 The features of INTEL 8085 It is an 8 bit processor. It is a single chip device with 40 pins. It has multiplexed address and data bus.(AD0- AD7). It works on 5 Volt dc power supply. The maximum clock frequency is 3 MHz while minimum frequency is 500kHz. It provides 16 address lines so it can access 2^16 =64Kb of memory. It provides 5 hardware interrupts : TRAP, RST 5.5, RST 6.5, RST 7.5,INTR. It provides Accumulator , one flag register , 6 general purpose registers and two special purpose registers(Stack Pointer , Program Counter).
- 4. Pin Diagram of 8085
- 5. Pin Description of 8085 AD0-AD7: Multiplexed Address and data lines. A8-A15: Tri-stated higher order address lines. ALE: Address latch enable is an output signal . It goes high when operation is started by processor . S0,S1: These are the status signals used to indicate type of operation. S1 S0 RESULT
- 6. Pin Description of 8085 : : :Read is active low input signal used to read data fromI/O device or memory : :Write is an active low output signal used write data onmemory or an I/O device READY : This an output signal used to check the statusof output device . If it is low, µP will WAIT until it ishigh. TRAP : It is an Edge triggered highest priority , nonmask able interrupt. After TRAP, restart occurs and execution starts from address 0024H.
- 7. Pin Description of 8085 INTR & INTA : is a interrupt request signal after which µP generates INTA or interrupt acknowledge IO/M¯: This is output pin or signal used to indicate whether 8085 is working in I/O mode(IO/M¯=1) or Memory mode(IO/M¯=0 ). RESTART INTERRUPTS; These three inputs have the same timing as INTR except they cause an internal RESTART to be automatically RST 7.5 ~~ Highest Priority RST 6.5 RST 5.5 -- Lowest Priority These interrupts have a higher priority than the
- 8. Pin Description of 8085 TRAP (Input) :Trap interrupt is a non maskable restart It is recognized at the same time as INTR. It is unaffected by any mask Interrupt Enable. It has highest priority of any interrupt. • HOLD&HLDA:HOLD is an input signal .When µP receives HOLD signal it completes current machine cycle and stops executing next instruction. In response to HOLD µP generates HLDA that is HOLD Acknowledge signal. RESET IN¯:This is input signal. When RESET IN¯ is low µp restarts and starts executing from location 0000H. X1X2 :These are clock input signals and are connected to external LC or RC circuit. These are divide by two so if 6 MHz is connected to X1X2, the operating frequency becomes 3 MHz VCC & VSS: Power supply VCC=+ 5Volt& VSS=GND reference.
- 10. Description of the Architecture Arithmetic and Logical Group Accumulator: It is 8 bit general purpose register. It is connected to ALU. So most of the operations are done in Accumulator. Temporary register: It is not available for user . All the arithmetic and logical operations are done in the temporary register but user can’t access it. Flag: It is a group of 5 flip flops used to know status of various operations done. The Flag Register along with Accumulator is called PSW or Program Status Word
- 11. Description of the Architecture Arithmetic and Logical Group S Z X AC X P X CY Flag Register is given by: S: Sign flag is set when result of an operation is negative. Z: Zero flag is set when result of an operation is 0. Ac: Auxiliary carry flag is set when there is a carry out of lower nibble or lower four bits of the operation. CY: Carry flag is set when there is carry generated by an operation. P:Parity flag is set when result contains even number of 1’s. Rest are don’t care flip flops.
- 12. Description of the Architecture Register Group Temporary registers (W,Z):These are not available for user. These are loaded only when there is an operation being performed. General purpose:There are six general purpose registers in 8085 namely B,C,D,E,H,L.These are used for various data Special purpose :There are two special purpose registers in 8085: SP :Stack Pointer. PC:Program Counter.
- 13. Description of the Architecture Register Group Stack Pointer: This is a temporary storage memory 16 bit register.Since there are only 6 general purpose registers, there is a need to reuse them .Whenever stack is to be used previous values are PUSHED on stack and then after the program is over these values are POPED back. Program Counter: It is 16 bit register used to point the location from which the next instruction is to be fetched. When a single byte instruction is executed PC is automatically incremented by 1.Upon reset PC contents are set to 0000H and next instruction is fetched onwards.
- 14. Memory interfacing of 8085 Microprocessor The Address and Data Busses The address bus has 8 signal lines A8 – A15 which are unidirectional. The other 8 address bits are multiplexed (time shared) with the 8 data bits.So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7 and D0 – D7 at the same time. During the execution of the instruction, these lines carry the address bits during the early part, then during the late parts of the execution, they carry the 8 data bits. In order to separate the address from the data, we can use a latch to save the value before the function of the bits changes.
- 15. Memory interfacing of 8085 Microprocessor The Control and Status Signals There are 4 main control and status signals: ALE: Address Latch Enable. This signal is a pulse that become 1 when the AD0 – AD7 lines have an address on them. It becomes 0 after that. This signal can be used to enable a latch to save the address bits from the AD lines. RD: Read. Active low.WR: Write. Active low. IO/M: This signal specifies whether the operation is a memory operation (IO/M=0) or an I/O operation (IO/M=1). S1 and S0 : Status signals to specify the kind of operation being performed
- 16. Memory interfacing of 8085 Microprocessor Demultiplexing AD7-AD0 ALE operates as a pulse during T1, we will be able to latch the address. Then when ALE goes low, the address is saved and the AD7– AD0 lines can be used for their purpose as the bi-directional data lines.
- 17. TIMING AND STATE DIAGRAM Op-code Fetch: It basically requires 4 T states from T1-T4 The ALE pin goes high at first T state always. AD0-AD7 are used to fetch OP-code and store the lower byte of Program Counter. A8-A15 store the higher byte of the Program Counter while IO/M¯ will be low since it is memory related operation. RD¯ will only be low at the Op-code fetching time. WR¯ will be at HIGH level since no write operation is done. S0=1,S1=1 for Op-code fetch cycle.
- 18. TIMING AND STATE DIAGRAM Op-code Fetch:
- 19. TIMING AND STATE DIAGRAM Memory Read Cycle: • It basically requires 3T states from T1-T3 . • The ALE pin goes high at first T state always. • AD0-AD7 are used to fetch data from memory and store the lower byte of address. • A8-A15 store the higher byte of the address while IO/M¯ will be low since it is memory related operation. • RD¯ will only be low at the data fetching time. • WR¯ will be at HIGH level since no write operation is done. • S0=0,S1=1 for Memory read cycle.
- 20. TIMING AND STATE DIAGRAM Memory Read Cycle:
- 21. TIMING AND STATE DIAGRAM Memory write Cycle: • It basically requires 3T states from T1-T3 . • The ALE pin goes high at first T state always • AD0-AD7 are used to fetch data from CPU and store the lower byte of address. • A8-A15 store the higher byte of the address while IO/M¯ will be low since it is memory related operation. • RD¯ will be HIGH since no read operation is done. • WR¯ will be at LOW level only when data fetching is done. • S0=1,S1=0 for Memory write cycle.
- 22. TIMING AND STATE DIAGRAM Memory write Cycle:
- 23. TIMING AND STATE DIAGRAM I/O read Cycle: • It basically requires 3T states from T1-T3 . • The ALE pin goes high at first T state always. • At falling edge of T1 the microprocessor outputs the bit address on both lower order lines AD0-AD7 and higher order address A8-A15 • while IO/M¯ will be high since it is I/O related operation. • In the second T state RD¯ will be low ,the I/O port is enabled for placing data on the data bus. • WR¯ will be at HIGH level since no write operation is done. • S0=0,S1=1 for I/O read cycle.
- 24. TIMING AND STATE DIAGRAM I/O read Cycle:
- 25. TIMING AND STATE DIAGRAM I/O write Cycle: • It basically requires 3T states from T1-T3 . • The ALE pin goes high at first T state always. • At falling edge of T1 the microprocessor outputs the bit address on both lower order lines AD0-AD7 and higher order address A8-A15 • while IO/M¯ will be high since it is I/O related operation. • RD¯ will be HIGH since no read operation is done. • WR¯ will be at LOW level only when data fetching is done. • S0=1,S1=0 for Memory write cycle.
- 26. TIMING AND STATE DIAGRAM I/O write Cycle:
- 27. Memory interfacing of 8085 Microprocessor
- 28. Memory interfacing of 8085 Microprocessor Generally µP 8085 can address 64 kB of memory . Generally EPROMS are used as program memory and RAM as data memory. We can interface Multiple RAMs and EPROMS to single µP . Memory interfacing includes 3 steps : Select the chip. Identify register. Enable appropriate buffer.
- 29. Memory interfacing of 8085 Microprocessor
- 30. Memory mapping of 8085 Microprocessor 8085 has 16 bit bus The complete address space is thus given by the range of addresses 0000H – FFFFH The range of address allocated to the memory device is known as it’s memory map .
- 31. Memory mapping of 8085 Microprocessor Memory map 64KB memory device: • Address line requires 16 (A0-A15) • Memory map 0000H-FFFFH Memory map 32KB memory device: • Address line requires 15 (A0-A14) • Depends on how the address line A15 is connected.
- 32. Memory mapping of 8085 Microprocessor A15 A14 A13 A12 A11 TO A0 0 0 0 0 0…..000 =0000H =7FFFH A15 A14 A13 A12 A11 TO A0 0 1 1 1 1…..111
- 33. Example 8085 Memory Interfacing Interface 2Kbytes of Memory to 8085 with starting address 8000H. Initially we realize that 2K memory requires 11 address lines (2^11=2048). So we use A0-A10 .
- 34. Example 8085 Memory Interfacing Address lines A0-A10 are used to interface memory while A11,A12,A13,A14,A15 are given to 3:8 Decoder to provide an output signal used to select the memory chip CS¯or Chip select input. MEMR¯ and MEMW¯ are given to RD¯ and WR¯ pins of Memory chip. Data lines D0-D7 are given to D0-D7 pins of the memory chip. In this way memory interfacing can be achieved
- 35. Example 8085 Memory Interfacing The diagram of 2k interfacing is shown below:
- 36. Example 8085 Memory Interfacing
- 37. Example 8085 Memory Interfacing
- 38. Interfacing IO devices with 8085 Memory mapped I/O • 8085 uses its 16-bit address bus to identify a memory location • Memory address space: 0000H to FFFFH • 8085 needs to identify I/O devices also I/O devices can be interfaced using addresses from memory space • 8085 treats such an I/O device as a memory location • This is called Memory-mapped I/O
- 39. Interfacing IO devices with 8085 Peripheral-mapped I/O • 8085 has a separate 8-bit addressing scheme for I/O devices • I/O address space: OOH to FFH • This is called Peripheral-mapped I/O or I/O-mapped I/O
- 40. Interfacing IO devices with 8085 8085 Communication with I/O devices Involves the following three steps • 1 Identify the I/O device (with address) • 2. Generate Timing & Control signals • 3. Data transfer takes place 8085 communicates with a I/O device only if there is a Program Instruction to do so
- 41. 8085 INTERRUPTS Interrupt is a process where an external device can get the attention of the microprocessor. • The process starts from the I/O device • The process is asynchronous.
- 42. 8085 INTERRUPTS TYPES Classification of Interrupts • Interrupts can be classified into two types: • Maskable Interrupts (Can be delayed or Rejected) • Non-Maskable Interrupts (Can not be delayed or Rejected) Interrupts can also be classified into: • Vectored (the address of the service routine is hard- wired) • Non-vectored (the address of the service routine needs to be supplied externally by the device)
- 43. 8085 INTERRUPTS TYPES The 8085 has 5 interrupt inputs. INTR • The INTR input is the only non-vectored interrupt. • INTR is maskable using the EI/DI instruction pair. RST • RST 5.5, RST 6.5, RST 7.5 are all automatically vectored. • RST 5.5, RST 6.5, and RST 7.5 are all maskable. TRAP • TRAP is the only non-maskable interrupt in the 8085 • TRAP is also automatically vectored
- 44. RESPONDING TO INTERRUPTS There are two ways of redirecting the execution to the ISR depending on whether the interrupt is vectored or non- vectored. • Vectored: The address of the subroutine is already known to the Microprocessor • Non Vectored: The device will have to supply the address of the subroutine to the Microprocessor
- 45. RESPONDING TO INTERRUPTS Non Vectored: The device will have to supply the address of the subroutine to the Microprocessor When a device interrupts, it actually wants the µP to give a service which is equivalent to asking the µP to call a subroutine. This subroutine is called ISR (Interrupt Service The ‘EI’ instruction is a one byte instruction and is used to Enable interrupts. The ‘DI’ instruction is a one byte instruction and is used to Disable interrupts. The 8085 has a single Non-Maskable interrupt.
- 46. 8085 PROGRAM EXAMPLE ADD OF TWO NUMBERS • 8000H MVIA,03H • 8002H MVIC,02H • 8004H ADD C • 8005H HLT 03H move to Accumulator Move value 02H to register B Addition a and c and move to accumulator End
- 47. 8085 PROGRAM EXAMPLE SUBSTRUCTION OF TWO NUMBERS • 8000H MVIA,08H • 8002H MVIC,07H • 8004H SUB C • 8005H HLT 03H move to Accumulator Move value 02H to register B Addition a and c and move to accumulator End
- 48. 8085 PROGRAM EXAMPLE SWAPING OF TWO NUMBERS • 8000H MVIB,04H • 8002H MVIC,06H • 8004H MVID,00H • 8006H MOV D,B • 8007H MOV B,C • 8008H MOV C,D • 8009H HLT 04H MOVE TO B 06H MOVE TO C 00H MVE TO D VALUE OF B MOVE TO D VALUE OF C MOVE TO B VALUE OF D MOVE TO C END
- 49. 8085 PROGRAM EXAMPLE STORE 05H TO 9000H LOAD TO THE ACCUMULATOR LOWER PART OF THE ADDRESS UPPER PART OF THE ADDRESS MOVE DATA ACCUMULATOR TO REGISTER D END LOAD A NUMBER TO A MEMORY LOCATION TO REGISTOR D • 9000H 05H • 8000H LDA • 8001H 00H • 8002H 90H • 8003H MOV D,A • 8004H HLT