![array accesses in a DAG
• An assignment from an array, like x = a [i], is represented by
creating a node with operator =[] and two children representing
the initial value of the array, a0 in this case, and the index i.
Variable x becomes a label of this new node.
• An assignment to an array, like a [j] = y, is represented by a new
node with operator []= and three children representing a0, j and y.
There is no variable labeling this node. What is different is that the
creation of this node kills all currently constructed nodes whose
value depends on a0. A node that has been killed cannot receive
any more labels; that is, it cannot become a common
subexpression.](https://image.slidesharecdn.com/presentation-240206055808-eb0e2631/85/PRESENTATION-ON-DATA-STRUCTURE-AND-THEIR-TYPE-15-320.jpg)
![Intermediate-code tree for a[i]=b+1](https://image.slidesharecdn.com/presentation-240206055808-eb0e2631/85/PRESENTATION-ON-DATA-STRUCTURE-AND-THEIR-TYPE-20-320.jpg)
PRESENTATION ON DATA STRUCTURE AND THEIR TYPE
- 1. COMPILER DESIGN BCA 5th Semester 2020 Topic: Code Generation Sakhi Bandyopadhyay Department of Computer Science and BCA Kharagpur College
- 2. Introduction • The final phase of a compiler is code generator • It receives an intermediate representation (IR) with supplementary information in symbol table • Produces a semantically equivalent target program • Code generator main tasks: • Instruction selection • Register allocation and assignment • Insrtuction ordering Front end Code optimizer Code Generator
- 3. Issues in the Design of Code Generator • The most important criterion is that it produces correct code • Input to the code generator • IR + Symbol table • We assume front end produces low-level IR, i.e. values of names in it can be directly manipulated by the machine instructions. • Syntactic and semantic errors have been already detected • The target program • Common target architectures are: RISC, CISC and Stack based machines • In this chapter we use a very simple RISC-like computer with addition of some CISC-like addressing modes
- 4. complexity of mapping • the level of the IR • the nature of the instruction-set architecture • the desired quality of the generated code. x=y+z LD R0, y ADD R0, R0, z ST x, R0 a=b+c d=a+e LD R0, b ADD R0, R0, c ST a, R0 LD R0, a ADD R0, R0, e ST d, R0
- 5. Register allocation • Two subproblems • Register allocation: selecting the set of variables that will reside in registers at each point in the program • Resister assignment: selecting specific register that a variable reside in • Complications imposed by the hardware architecture • Example: register pairs for multiplication and division t=a+b t=t*c T=t/d t=a+b t=t+c T=t/d L R1, a A R1, b M R0, c D R0, d ST R1, t L R0, a A R0, b M R0, c SRDA R0, 32 D R0, d ST R1, t
- 6. A simple target machine model • Load operations: LD r,x and LD r1, r2 • Store operations: ST x,r • Computation operations: OP dst, src1, src2 • Unconditional jumps: BR L • Conditional jumps: Bcond r, L like BLTZ r, L
- 7. Target program for a sample call and return
- 8. Stack Allocation Return to caller in Callee: BR *0(SP) in caller: SUB SP, SP, #caller.recordsize Branch to called procedure
- 9. Target code for stack allocation
- 10. Basic blocks and flow graphs • Partition the intermediate code into basic blocks • The flow of control can only enter the basic block through the first instruction in the block. That is, there are no jumps into the middle of the block. • Control will leave the block without halting or branching, except possibly at the last instruction in the block. • The basic blocks become the nodes of a flow graph
- 11. Flow graph based on Basic Blocks
- 12. DAG representation of basic blocks • There is a node in the DAG for each of the initial values of the variables appearing in the basic block. • There is a node N associated with each statement s within the block. The children of N are those nodes corresponding to statements that are the last definitions, prior to s, of the operands used by s. • Node N is labeled by the operator applied at s, and also attached to N is the list of variables for which it is the last definition within the block. • Certain nodes are designated output nodes. These are the nodes whose variables are live on exit from the block.
- 13. DAG for basic block
- 14. DAG for basic block
- 15. array accesses in a DAG • An assignment from an array, like x = a [i], is represented by creating a node with operator =[] and two children representing the initial value of the array, a0 in this case, and the index i. Variable x becomes a label of this new node. • An assignment to an array, like a [j] = y, is represented by a new node with operator []= and three children representing a0, j and y. There is no variable labeling this node. What is different is that the creation of this node kills all currently constructed nodes whose value depends on a0. A node that has been killed cannot receive any more labels; that is, it cannot become a common subexpression.
- 16. DAG for a sequence of array assignments
- 17. Rules for reconstructing the basic block from a DAG • The order of instructions must respect the order of nodes in the DAG. That is, we cannot compute a node's value until we have computed a value for each of its children. • Assignments to an array must follow all previous assignments to, or evaluations from, the same array, according to the order of these instructions in the original basic block. • Evaluations of array elements must follow any previous (according to the original block) assignments to the same array. The only permutation allowed is that two evaluations from the same array may be done in either order, as long as neither crosses over an assignment to that array. • Any use of a variable must follow all previous (according to the original block) procedure calls or indirect assignments through a pointer. • Any procedure call or indirect assignment through a pointer must follow all previous (according to the original block) evaluations of any variable.
- 18. Flow graph of an inner loop
- 19. Code sequence using global register assignment
- 20. Intermediate-code tree for a[i]=b+1
- 23. Optimal three-register code using only two registers
- 24. Syntax tree for (a-b)+c*(d/e) with cost vector at each node
- 25. minimum cost of evaluating the root with two registers available • Compute the left subtree with two registers available into register R0, compute the right subtree with one register available into register R1, and use the instruction ADD R0, R0, R1 to compute the root. This sequence has cost 2+5+1=8. • Compute the right subtree with two registers available into R l , compute the left subtree with one register available into R0, and use the instruction ADD R0, R0, R1. This sequence has cost 4+2+1=7. • Compute the right subtree into memory location M, compute the left subtree with two registers available into register RO, and use the instruction ADD R0, R0, M. This sequence has cost 5+2+1=8.
- 26. Thank You