Project report of 2016 Trainee_final

A REPORT ON
Design & Implementation of Digital Circuits on Kintex-7
FPGA based KC705 Evaluation Kit
Submitted to: Mr. AMITAVA ROY
Computer Division
Vocational Training at
Variable Energy Cyclotron Centre, Kolkata
From: 11th
July to 10th
August
Submitted By-
AKASH CHOWDHURY
Electronics & Communication Engineering - B.Tech – 4th
Year
of
HERITAGE INSTITUTE OF TECHNOLOGY

ACKNOWLEDGEMENT
I would like to extend my heartfelt gratitude to our project guide, Mr.Ram
Kumar Paul. Without his valuable support and guidance this project would not
have got proper shape.
I also thank my supervisors Mr.Partha Dhara and Mr.Tanushyam
Bhattacharya for their constant source of encouragement during the course of
preparation of this report.
I am also grateful to my training coordinator Dr. P Y Nabhiraj for his guidance
and support. Without him the training program would not have been possible.

TABLE OF CONTENTS
1.Abstract
2.Introduction
 FPGA
 Architecture
 Features
3.Program overview
 Hardware Description Language
 VHDL
 Programming Structure
4.Development platform
5.Simulation and Implementation Details
6. Conclusion
7. Reference

Abstract
In this project work we have designed & simulated the output of
various logic circuits using Xilinx ISE Design Suite 14.7 EDA tool
and VHDL as programming language. We have tested the
performance of our design on Kintex-7 FPGA based KC-705
evaluation board.

INTRODUCTION
Field Programmable Gate Array popularly known as FPGA is a good choice of
digital logic design. They are prefabricated silicon chips that can be
programmed electrically to implement any digital design.
The basic architecture of FPGA consists of three major components:
programmable logic blocks which implements the logic functions,
programmable routing (interconnects) to implement these functions and I/O
blocks to make off-chip connections. An illustration of typical FPGA
architecture is shown in figure
Fig.1 Internal Architecture of FPGA
 Programmable Logic Blocks (PLB)
The purpose of programmable logic block in a FPGA is to provide the basic
computation and storage elements used in digital systems. The basic logic
element contains some form of programmable combinational logic, a flip-flop
or latch and some fast carry logic to reduce area and delay cost to it could be
entire processor. In addition to a basic logic block, many modern FPGAs
contains a heterogeneous mixture of different blocks, some of which can only
be used for specific functions, such as dedicated memory blocks, multipliers or
multiplexers; of course, configuration memory is used throughout the logic
block to control the specific function of each element within the block.
 Programmable Interconnect
The programmable routing in an FPGA provides connections among logic
blocks and I/O blocks to complete a user defined design. It consists of

multiplexers, pass transistors and tri-state buffers, which forms the desired
connection. Generally, pass transistors and multiplexers are used within a logic
cluster to connect the logic elements together while all three are used for more
global routing structures.
 Programmable I/O
The media or mean required to interface the logic blocks and routing
architectures to the wide range of external components to FPGA called as I/O
pads or programmable I/O. The I/O pad and surrounding supporting logic
circuitry forms as an I/O cells. One of the most important decisions in I/O
architecture design is the selection of standards that will be supported. This
involves carefully made trade-offs because, unlike LUTs, which can implement
any digital functions, I/O cells can generally implement the voltage standards
selected by designers. Supporting large number of standards can increase the
silicon area required for I/O cells significantly. Additionally to support more
number of standards pin capacitance may increase with more number of pins,
which can limit the performance.
Features
 FPGA design ASIC circuit (ASIC), the user does not need to cast film
production; you can get a combination of the chip.
 FPGA can do full custom or semi-custom ASIC circuits in the sample
piece.
 FPGA internal trigger and I / O pins.
 FPGAs, ASIC circuits in the shortest design cycle, the lowest
development costs, one of the smallest devices in the risk.
 FPGA using high-speed CMOS technology, low power consumption,
compatible with CMOS, TTL level.

Program overview
In electronics, a hardware description language (HDL) is a specialized computer
language used to describe the structure and behaviour of electronic circuits, and
most commonly, digital logic circuits. One important difference between most
programming languages and HDLs is that HDLs explicitly include the notion of
time.
A hardware description language enables a precise, formal description of an
electronic circuit that allows for the automated analysis and simulation of an
electronic circuit. It also allows for the synthesis of a HDL description into a net
list (a specification of physical electronic components and how they are
connected together), which can then be placed and routed to produce the set of
masks used to create an integrated circuit.
HDLs form an integral part of Electronic Design Automation (EDA) systems,
especially for complex circuits, such as application-specific integrated
circuits, microprocessors, and programmable logic devices.
Very High Speed Integrated Circuit Hardware Description
Language(VHDL)
VHDL is commonly used to write text models that describe a logic circuit. Such
a model is processed by a synthesis program, only if it is part of the logic
design. A simulation program is used to test the logic design using simulation
models to represent the logic circuits that interface to the design. This collection
of simulation models is commonly called a test bench.
VHDL allows arrays to be indexed in either ascending or descending direction;
both conventions are used in hardware, whereas in Ada and most programming
languages only ascending indexing is available.
VHDL has filed input and output capabilities, and can be used as a general-
purpose language for text processing, but files are more commonly used by a
HDL
ABEL VERILOG VHDL

simulation test bench for stimulus or verification data. There are some VHDL
compilers which build executable binaries.
In this case, it might be possible to use VHDL to write a test bench to verify the
functionality of the design using files on the host computer to define stimuli, to
interact with the user, and to compare results with those expected. One
particular pitfall is the accidental production of transparent latches rather
than D-type flip-flops as storage elements.
A final point is that when a VHDL model is translated into the "gates and wires"
that are mapped onto a programmable logic device such as a CPLD or FPGA,
and then it is the actual hardware being configured, rather than the VHDL code
being "executed" as if on some form of a processor chip. Jayaram Bhasker
writes, “VHDL is a large and complex language with many complex constructs
that have complex semantic meanings..”
 Programming Structure
In VHDL, a design consists at a minimum of an entity which describes the
interface and an architecture which contains the actual implementation. In
addition, most designs import library modules. Some designs also contain
multiple architectures and configurations.
Fig.2 VHDL Design Flow

Entity and Architecture are the two main basic programming structures in
VHDL.
Entity
Entity can be seen as the black box view of the system. We define the inputs
and outputs of the system which we need to interface.
Entity AND GATE is
Port (
A: in std_logic;
B: in std_logic;
Y: out std_logic;
);
end AND GATE;
Entity name AND GATE is given by the programmer; each entity must have a
name. There are certain naming conventions which will be explained later in the
tutorial.

Architecture
Architecture defines what is in our black box that we described using ENTITY.
We can use either behavioural or structural models to describe our system in the
architecture. In Architecture we will have interconnections, processes,
components, etc.
Architecture AND1 of AND GATE is
--declarations
Begin
--statements
Y <= A AND B;
End architecture AND1;
Entity name or architecture name is user defined. Identifiers can have uppercase
alphabets, lowercase alphabets, and numbers and underscore (_).First letter of
identifier must be an alphabet and identifier cannot end with an underscore. In
VHDL, keywords and user identifiers are case insensitive. VHDL is strongly
typed language i.e. every object must be declared

Development Platform
The Kintex-7 FPGA based KC705 Evaluation Kit includes all the basic
components of hardware, design tools, IP, and pre-verified reference designs
including a targeted design enabling high-performance serial connectivity and
advanced memory interfacing. The included pre-verified reference designs and
industry-standard FPGA Mezzanine Connectors (FMC) allow scaling and
customization with daughter cards.
Fig.3 KC705 Evaluation Kit

Simulation and Implementation Details
SL NO. Programs
1. Half Adder
2. Full Adder
3. Multiplexer
4. 4 Input AND Gate
5. 16 bit Counter
6. Finite State Machine
7. Subtractor using Xilinx IP
8. Multiplier using Xilinx IP

1. HALF ADDER: -
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity half_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC
);
end half_adder;
architecture Behavioral of half_adder is
begin
s <=a xor b;
c <=a and b;
end Behavioral;

SIMULATED OUTPUT
A B S C
1. 1 1 0 1
2. 0 1 1 0
3. 1 0 1 0
4. 0 0 0 0

2. FULL ADDER
library IEEE;
entity adder_full is
b : in STD_LOGIC;
c : in STD_LOGIC;
f : out STD_LOGIC;
o : out STD_LOGIC);
end adder_full;
architecture Behavioral of adder_full is
signal d :STD_LOGIC;
signal e: STD_LOGIC;
signal g : STD_LOGIC;
begin
d <=a xor b;
e <=a and b;
f <=d xor c;
g <=d and c;
o <=g or e;
end Behavioral;

SIMULATED OUTPUT
A B C F O
1. 1 1 0 0 1
2. 0 1 0 1 0
3. 1 0 0 1 0
4. 0 0 0 0 0
5. 1 1 1 1 1
6. 0 1 1 0 1
7. 1 0 1 0 1
8. 0 0 1 1 0
1
.
2
3
4
5
6
7
8

3.MULTIPLEXER
library IEEE;
entity mux is
b : in STD_LOGIC;
c : in STD_LOGIC;
--d : inout STD_LOGIC;
--e : inout STD_LOGIC;
--f : inout STD_LOGIC;
o : out STD_LOGIC
);
end mux;
architecture arch of mux is
SIGNAL d: STD_LOGIC;
SIGNAL e: STD_LOGIC;
SIGNAL f: STD_LOGIC;
begin
d <= a nand b;
e <= b nand b;
f <= e nand c;
o <= d nand f;
end arch;

SIMULATED OUTPUT
A B C O
1. 0 0 1 0
2. 1 0 1 1
3. 1 1 1 1
4. 0 1 1 1
5. 1 0 0 0
6. 0 0 0 0
7. 1 1 0 0
8. 0 1 0 1
1 2
3
4
5
6
7
8

4.4INPUT AND GATE
library IEEE;
entity and_4 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
c : out STD_LOGIC);
end and_4;
architecture Behavioral of and_4 is
begin
c<=a(0) and a(1) and a(2) and a(3);
end Behavioral;
SIMULATED OUTPUT
A(0) A(1) A(2) A(3) C
1. 0 0 0 0 0
2. 1 1 1 1 1
1 2

5.16 BIT COUNTER
library IEEE;
use IEEE.std_logic_unsigned.all;
entity counter_15bit is
Port (
clk:in STD_LOGIC;
q,qbar: inout std_logic_vector(15 downto 0)
);
end counter_15bit;
architecture Behavioral of counter_15bit is
component jk
Port (
j: in STD_LOGIC;
k: in STD_LOGIC;
clk :in STD_LOGIC;
q,qbar :out STD_LOGIC
);
end component;
signal a:std_logic;
signal b:std_logic;
signal c:std_logic;
signal d:std_logic;
signal e:std_logic;
signal f:std_logic;
signal g:std_logic;
signal h:std_logic;
signal i:std_logic;
signal j:std_logic;
signal k:std_logic;
signal l:std_logic;
signal m:std_logic;
signal n:std_logic;
signal o:std_logic;
signal p:std_logic;
begin
a<=q(0);
b<=q(0) and q(1);
c<=q(0) and q(1) and q(2);
d<=q(0) and q(1) and q(2) and q(3);
e<=q(0) and q(1) and q(2) and q(3) and q(4);
f<=q(0) and q(1) and q(2) and q(3) and q(4) and q(5);
g<=q(0) and q(1) and q(2) and q(3) and q(4) and q(5) and q(6);
h<=q(0) and q(1) and q(2) and q(3) and q(4) and q(5) and q(6) and q(7);

i<=q(0) and q(1) and q(2) and q(3) and q(4) and q(5) and q(6) and q(7) and q(8);
j<=q(0) and q(1) and q(2) and q(3) and q(4) and q(5) and q(6) and q(7) and q(8) and q(9);
k<=q(0) and q(1) and q(2) and q(3) and q(4) and q(5) and q(6) and q(7)and q(8) and q(9) and q(10);
l<=q(0) and q(1) and q(2) and q(3) and q(4) and q(5) and q(6) and q(7) and q(8) and q(9) and q(10)
and q(11);
m<=q(0) and q(1) and q(2) and q(3) and q(4) and q(5) and q(6) and q(7) and q(8) and q(9) and q(10)
and q(11) and q(12);
n<=q(0) and q(1) and q(2) and q(3) and q(4) and q(5) and q(6) and q(7) and q(8) and q(9) and q(10)
and q(11) and q(12) and q(13);
o<=q(0) and q(1) and q(2) and q(3) and q(4) and q(5) and q(6) and q(7) and q(8) and q(9) and q(10)
and q(11) and q(12) and q(13) and q(14);
p<=q(0) and q(1) and q(2) and q(3) and q(4) and q(5) and q(6) and q(7) and q(8) and q(9) and q(10)
and q(11) and q(12) and q(13) and q(14) and q(15);
a1:JK port map('1','1',clk,q(0),qbar(0));
a2:JK port map(a,a,clk,q(1),qbar(1));
a3:JK port map(b,b,clk,q(2),qbar(2));
a4:JK port map(c,c,clk,q(3),qbar(3));
a5:JK port map(d,d,clk,q(4),qbar(4));
a6:JK port map(e,e,clk,q(5),qbar(5));
a7:JK port map(f,f,clk,q(6),qbar(6));
a8:JK port map(g,g,clk,q(7),qbar(7));
a9:JK port map(h,h,clk,q(8),qbar(8));
a10:JK port map(i,i,clk,q(9),qbar(9));
a11:JK port map(j,j,clk,q(10),qbar(10));
a12:JK port map(k,k,clk,q(11),qbar(11));
a13:JK port map(l,l,clk,q(12),qbar(12));
a14:JK port map(m,m,clk,q(13),qbar(13));
a15:JK port map(n,n,clk,q(14),qbar(14));
a16:JK port map(o,o,clk,q(15),qbar(15));
end Behavioral;
JK FF
library IEEE;
entity JK is
Port ( J : in STD_LOGIC;
K : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC;
qbar:out std_logic);
end JK;
architecture Behavioral of JK is
signal input:std_logic_vector(1 downto 0);
begin

input<=j&k;
u1:process(clk,J,K)
variable temp:std_logic:='0';
begin
if(clk='1' and clk'event) then
case input is
when "10"=>temp:='1';
when "01"=>temp:='0';
when "11"=>temp:=not temp;
when others=>null;
end case;
end if;
q<=temp;
qbar<=not temp;
end process u1;
end Behavioral;

6. FSM
library IEEE;
entity fsm_test is
PORT (clk:in STD_LOGIC;
P:in STD_LOGIC;
Q:in std_logic;
R:in std_logic;
S:in std_logic;
reset:in STD_LOGIC;
led:out std_logic_vector(0 to 6)
);
end fsm_test;
architecture Behavioral of fsm_test is
TYPE Apoorva IS (A,B,C,D);
SIGNAL State :Apoorva;
begin
PROCESS (clk,reset,P,Q,R,S)
begin
If(reset = '1') THEN State <= A;
elsif(clk='1' and clk'event)then
Case State is
when A=>
led<="0001111";
if(P='1') THEN State <= B;
end if;
when B=>
led<="0011111";
if(Q='1') then State <=C;
end if;
when C=>
led<="0111111";
if(R='1')then State <=D;
end if;
when D=>
led<="1111111";
if(S='1')then State <=A;
end if;
when others =>
State <=A;
end case;
end if;
end process;
end Behavioral;

SIMULATED OUTPUT
Reset=1
P=1
S=1
Q=1
R=1
A
D
C
B

7. MULTIPLIER
library IEEE;
entity cycle is
port(
a:in std_logic_vector(3 downto 0);
b:in std_logic_vector(3 downto 0);
clk:in std_logic;
p:out std_logic_vector(7 downto 0)
);
end cycle;
architecture Behavioral of cycle is
component test_cyclotron is
port (
clk:in std_logic;
p:out std_logic_vector(7 downto 0)
);
end component;
begin
u2:test_cyclotron port map
(
a=>a,
b=>b,
clk=>clk,
p=>p
);
end Behavioral;

8.SUBTRACTOR USING IP
library IEEE;
entity new_ip_subtractor is
port(
clk:in std_logic;
s:out std_logic_vector(3 downto 0)
);
end new_ip_subtractor;
architecture Behavioral of new_ip_subtractor is
component ip_subtractor is
port(
clk:in std_logic;
s:out std_logic_vector(3 downto 0)
);
end component;
begin
u1:ip_subtractor port map(
a=>a,
b=>b,
clk=>clk,
s=>s
);
end Behavioral;

Conclusion
The intent of this project work is to introduce VHDL and its basic concepts to the engineers who will
be using the language to describe circuits for implementation and simulation in programmable
logic.VHDL is a programming language that has been designed and optimized for describing the
behaviour of digital circuits and systems.
To this end, we will avoid prolonged discussions that are appropriate only for developers of
simulation models and system-level simulations, and concentrate instead on those aspects of the
language that are most useful for circuit synthesis. By the help of this project the students will get
friendly to this language and language features are motivated by the need to describe specific aspects
of the operation of digital circuits, for example, events, propagation delays, and concurrency.

Reference
 Accelerating Computation with Field-Programmable Gate Arrays. Published by Springer,
P.O. Box 17, 3300 AA Dordrecht, The Netherlands.
 A VHDL Primer by Jayaram Bhasker.
 Stephen Brown, Zvonko Vranesic-Fundamentals of Digital Logic with VHDL Design
with CD-ROM-McGraw-Hill Science_Engineering_Math (2009).

Project report of 2016 Trainee_final

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