![SR LATCH ACTIVE HIGH
This SR latch is sometimes referred
as direct coupled RS flipflop.
• In an active high SR Latch two cross
coupled NOR gates are used.
• When the SET input goes high , the
output also goes high.[SET]
• When the SET input returns to low ,
however the output remains
High.[HOLD]
• The output stays High until the
RESET input goes High.
MAJOR PROBLEM:
In an S-R Latch ,activation of S input sets
the circuit, while activation of R input
resets the circuit. If both S and R inputs
are activated simultaneously , the circuit
will be in an invalid condition.
KEY POINT:
Active high is S based when S and R are
contrary to each other.](https://image.slidesharecdn.com/sequentialcircuitsautosaved2-211203041812/85/SEQUENTIAL-LOGIC-CIRCUITS-FLIP-FLOPS-AND-LATCHES-8-320.jpg)
![SR LATCH ACTIVE LOW
• In an active low SR Latch two cross
coupled NAND gates are used.
• When the RESET input goes high ,
the output Q also goes high.[SET]
• When the RESET input returns to low,
the output Q also returns to
low.[RESET]
• When both the inputs are high , then
the
output Q will remains same.[HOLD]
MAJOR PROBLEM:
If both S and R inputs are low , then
the circuit will be in an invalid
condition.
KEY POINT:
Active low is R based when S and R are
contrary to each other.](https://image.slidesharecdn.com/sequentialcircuitsautosaved2-211203041812/85/SEQUENTIAL-LOGIC-CIRCUITS-FLIP-FLOPS-AND-LATCHES-10-320.jpg)
![D FLIP-FLOP
• A D flip flop is by far the most important
of all the clocked flip-flops.
• It is used to create a delay in the circuit.
• It is a modification of SR clocked flipflop
with the addition of an inverter to prevent
S and R inputs from being at the same
logic level.
• The next state of the flip flop is the same
as the D input and is independent of the
present state.
• if the data input is held HIGH the flip flop
would be “SET” and when it is low the
flipflop would change and become
“RESET”.[Clock is 1 for both the
conditions].](https://image.slidesharecdn.com/sequentialcircuitsautosaved2-211203041812/85/SEQUENTIAL-LOGIC-CIRCUITS-FLIP-FLOPS-AND-LATCHES-17-320.jpg)
SEQUENTIAL LOGIC CIRCUITS (FLIP FLOPS AND LATCHES)
- 1. SEQUENTIAL CIRCUITS LATCHES AND FLIP-FLOPS Presentation by: C.MURALIDHARAN A.SUBHA SHREE V.A.SAIRAM
- 2. SEQUENTIAL CIRCUITS • DEFINITION: A Sequential Circuit is a combinational logic circuit that consists of inputs variable(X),logic gates(computational circuits)and the output variable (Z).
- 3. SEQUENTIAL CIRCUITS CONTD... • A combinational logic circuit produces an output based on present input values but a sequential logic circuit produces an output based on current input and also previous input values. • The latches and the flip flops are the building blocks of the sequential circuits. One latch or flip flop can store one bit of information. • There are basically four main types of latches and flip flops: SR,D,JK and T. • MEMORY ELEMENTS: Sequential circuits include memory elements that are capable of storing binary information. The basic memory element in sequential logic circuits is
- 4. TYPES OF SEQUENTIAL CIRCUITS • There are two main types of sequential circuits.Their classification depends on the timing of their signals. Synchronous sequential circuits Asynchronous sequential circuits Synchronous sequential circuits use level inputs and clock signals as the circuit inputs having limitations on the circuit propagation time and pulse width to generate the output. Asynchronous sequential circuits perform their operation without depending on the clock signals but use the input pulses and generate the output.
- 5. DIFFERENCE BETWEEN LATCHES & FLIP-FLOP LATCHES • Latches do not have a clock signal. • Works with only binary input. • Level triggered • Asynchronous • Operation is faster in latches. FLIP –FLOPS • Flip flop always has a clock signal. • Works with binary input as well as the clock signal. • Edge triggered. • Synchronous • Operation is comparatively slower due to clock signal.
- 6. APPLICATIONS OF SEQUENTIAL CIRCUITS • Shift registers • Flip Flops • Analog to digital and digital to analog converters • Counters • Clocks • Used as registers inside microprocessors and controllers to store temporary information.
- 7. TABLE OF CONTENTS • SR latch (Active high) • SR latch (Active low) • SR Flip-flop(Active high) • SR Flip-flop(Active low) • D Flip-flop • Master slave flip-flop • JK Flip-flop • T Flip-flop THIS INDICATES THAT THE KEY IS IN “ ON” CONDITION . i.e 1 THIS INDICATES THAT THE KEY IS IN “OFF” CONDITION. i.e 0 IMPORTANT POINT:
- 8. SR LATCH ACTIVE HIGH This SR latch is sometimes referred as direct coupled RS flipflop. • In an active high SR Latch two cross coupled NOR gates are used. • When the SET input goes high , the output also goes high.[SET] • When the SET input returns to low , however the output remains High.[HOLD] • The output stays High until the RESET input goes High. MAJOR PROBLEM: In an S-R Latch ,activation of S input sets the circuit, while activation of R input resets the circuit. If both S and R inputs are activated simultaneously , the circuit will be in an invalid condition. KEY POINT: Active high is S based when S and R are contrary to each other.
- 9. ACTIVE HIGH SET ACTIVE HIGH RESET From the truth table , we infer that for SET condition , input of S should be 1 and input of R is 0 then the Q value will be 1 and the LED of Q will glow. From the truth table , we infer that for RESET condition , input of S value is 0 and input of R is 1.Here the complement of Q will be 1 and LED of Q complement glows.
- 10. SR LATCH ACTIVE LOW • In an active low SR Latch two cross coupled NAND gates are used. • When the RESET input goes high , the output Q also goes high.[SET] • When the RESET input returns to low, the output Q also returns to low.[RESET] • When both the inputs are high , then the output Q will remains same.[HOLD] MAJOR PROBLEM: If both S and R inputs are low , then the circuit will be in an invalid condition. KEY POINT: Active low is R based when S and R are contrary to each other.
- 11. ACTIVE LOW SET ACTIVE LOW RESET From the truth table , we infer that for SET condition , input of S is 0 and input of R is 1 then the Q value will be 1 and LED of output Q glows. From the truth table , we infer that for RESET condition , input of S is 1 and input of R is 0 then the Q complement will be 1 and LED of Q complement glows.
- 12. SR FLIP-FLOP • The basic flipflop as it stands is an asynchronous sequential circuit . By addig gates to the inputs of the basic circuit , the flipflop can be made to respond to input levels during the occurrence of a clock pulse. • It consists of: • Two NOR gates and two AND gates along with a clock for ACTIVE HIGH SR • Four NAND gates along with a clock for ACTIVE LOW SR • The inputs are S ,R , and the clock .The outputs are Q and Q complement.
- 13. ACTIVE HIGH SR FLIP-FLOP • The circuit is formed by adding two AND gates to NOR based SR flipflop. • A clock pulse is given as input to both the extra AND gates.
- 14. ACTIVE HIGH SET ACTIVE HIGH RESET For SET condition , input of S should be 0 , input of R is 1 and clock pulse is 1 then the Q value will be 1 and the LED of Q will glow. For RESET condition , input of S value is 1, input of R is 0 and the clock pulse is 1.Here the complement of Q will be 1 and LED of Q complement glows.
- 15. ACTIVE LOW SR FLIP-FLOP • The circuit is formed by adding two NAND gates to NAND based SR flipflop. • A clock pulse is given as input to both the extra NAND gates.
- 16. ACTIVE LOW SET ACTIVE LOW RESET For SET condition , input of S is 1 , input of R is 0 and clock is set to 1 then the Q value will be 1 and LED of output Q glows. For RESET condition , input of S is 0 , input of R is 1 and clock is 1 then the Q complement will be 1 and LED of Q complement glows.
- 17. D FLIP-FLOP • A D flip flop is by far the most important of all the clocked flip-flops. • It is used to create a delay in the circuit. • It is a modification of SR clocked flipflop with the addition of an inverter to prevent S and R inputs from being at the same logic level. • The next state of the flip flop is the same as the D input and is independent of the present state. • if the data input is held HIGH the flip flop would be “SET” and when it is low the flipflop would change and become “RESET”.[Clock is 1 for both the conditions].
- 18. D FLIP-FLOP ACTIVE HIGH • For Active High D flipflop , two AND gates and two NOR gates are being used along with an inverter and a clock. • The D input directly goes to the AND gate(U11) and its complement goes to the other AND gate(U12).
- 19. ACTIVE HIGH 0-I/P ACTIVE HIGH 1-I/P Here the data input is given as 0 and the clock input is 1 .The output value 1 is received at Q and so the LED of Q glows. Here both the clock input and the data input is 1.The output value 1 is received at the Q complement and so the LED of Q complement glows here NOTE: I/P-
- 20. D FLIP-FLOP ACTIVE LOW • For Active Low D Flip-Flop, four NAND gates along with an inverter and a clock is being used. • The first two NAND gates (i.e U2 and U3) form a basic flip flop and gates U8 and U9 modify it into a clocked RS FLIPFLOP. • Here the D input goes to the NAND gate (U8) and its complement to the other NAND gate(U9).
- 21. ACTIVE LOW 0-I/P ACTIVE LOW 1-I/P Here the data input is given as 0 and the clock input is 1 .The output value 1 is received at Q complement and so the LED of Q complement glows. Here the data input is given as 1 and the clock input is 1 .The output value 1 is received at Q and so the LED of Q glows. NOTE: I/P- Input
- 22. MASTER SLAVE FLIP-FLOP • A master slave flipflop is constructed from two separate flipflops. • One circuit serves as a master and the other as a slave. • A clock and an inverter is present in the circuit. • The output from the master flipflop is connected to the two inputs of the slave flipflop. • Each flipflop is connected to a clock pulse complementary to each other. • If the clock pulse is in high state , the master flip flop is in ENABLE state and the slave flipflop is in DISABLE state. • If the clock pulse is in low state , the master flipflop is in DISABLE state and the slave flipflop is ENABLE state. • The types of Master Slave flipflop are listed below: • Master slave SR flipflop • Master slave JK flipflop The above diagram is Master slave SR flipflop.
- 23. JK FLIP-FLOP • A JK flipflop is a refinement of the RS flipflop. • Inputs J and K behave like S and R J-SET and K-CLEAR • It is one of the most useful and versatile flipflop. • The unique features are: If the J and K inputs are both at 1 and the clock pulse is applied , then the output will change state ,regardless of its previous condition. If both J and K inputs are at 0 and the clock pulse is applied there will be no change in the output. There is no indeterminate condition in the operation of JK flipflop.
- 24. JK FLIP-FLOP SET JK FLIP-FLOP RESET Here J input is 1 and K input is 0 and the clock pulse is 1 and so the output 1 is received at Q hence LED of Q glows. Here J is 0 , K is 1 and the clock pulse is also 1.The output 1 is received at Q complement and so LED of Q complement glows.
- 25. JK FLIP-FLOP PGT AND NGT • PGT is Positive Going Transition when clock pulse goes from 0 to 1 • NGT is Negative Going Transition when clock pulse goes from 1 to 0 • NGT is represented using a BUBBLE. • Transitions are also called Edges
- 26. JK FLIP-FLOP HOLD & TOGGLE • If both the J and K inputs are HIGH at logic 1 when the clock input also goes HIGH ,the circuit will be TOGGLED from SET state to a RESET state(i.e where 0 becomes 1 and 1 becomes 0). • At J=K=0 output continuous to be in the same state. This is the HOLD condition.
- 27. T FLIP-FLOP • The T flipflop is a single input version of JK flipflop. • The T flipflop is obtained from a JK type if both the inputs are tied together. • The designation T comes from the ability of the flipflop to “TOGGLE” . • Regardless of the present state of the flipflop , it assumes the complement state when the clock pulse occurs while input T is logic 1. • T flipflop can be designed from SR ,JK and D flipflop because T flipflop is not available as ICs. • But mostly we use JK flipflop to get T flipflop. • Hence it is also referred as single input JK flipflop and it is considered to be the simplest construction among all other flipflops. • T is TOGGLE INPUT
- 28. SUMMARY:
- 29. 1) C.MURALIDHARAN Assistant Professor , Biomedical Engineering , Rajalakshmi Engineering College 2) A.SUBHA SHREE Student , Biomedical Engineering , Rajalakshmi Engineering College 3) V.A.SAIRAM Student , Biomedical Engineering , Rajalakshmi Engineering College
- 30. THANK YOU