Simulation Using Isim
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This document provides an overview of using the Isim simulator to simulate VHDL designs. It describes creating a new project in Xilinx ISE, writing VHDL code, checking for syntax errors, and performing an interactive simulation. The simulation involves forcing clock and constant inputs, zooming the waveform display, and viewing variables within processes. The overall objective is to learn the basic flow for using the Isim simulator to compile and simulate a VHDL design.
Simulation Using Isim
- 1. Simulation Using Isim by: Samuel Neseem Mina Yousry
- 2. Copyrights Copyright © 2012 to authors. All rights reserved • All content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Samuel Neseem and Mina Yousry or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws. • Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses. • Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact. • Product names and trademarks mentioned in this presentation belong to their respective owners. 2
- 3. Objective • Using Isim to compile and simulate a given design unit • Skills gained: – Identify basic Simulator flow 3
- 4. Outline • Creating Project – Writing VHDL code – Checking syntax • Interactive Simulation 4
- 5. Creating Project Step 1: Open Xilinx ISE -> File > New Project
- 6. Creating Project Cont’d. Step 2: Set Project Location And Project Name as shown then press Next
- 7. Creating Project Cont’d. Step 3: • Set simulator options to Isim then press Next -> finish
- 8. Write VHDL Code Step 1: Right click on project node then select New Source Note: if you have an existing VHDL file you can select Add Source Step 2: - Set File Name and Location - Select VHDL Module then press Next
- 9. Write VHDL Code Cont’d. Step 3: press Next Note: -you can change entity name and architecture name -also you can add ports as shown and then press Next -> finish
- 10. Write VHDL Code Cont’d. Step 4: Write your VHDL code here
- 11. Check Syntax To Check Syntax Follow Steps as shown Note: if there is any error it will appear Here
- 12. Simulation To Open simulation window Follow Steps as shown
- 13. Simulation Cont’d. 1-Project ports and signals 2-Zooming 3-Restart 4-Run for the time specified on the toolbar
- 14. Simulation Cont’d. Force clock to i/p port: Right click on the port then select Force clock Then set options and press OK
- 15. Simulation Cont’d. Force constant value to i/p port: Right click on the port then select Force constant Then set the value and press OK
- 17. Simulation Cont’d. To show Variables in a proces Follow Steps as shown where #3 is process in your project
- 18. Contacts • You can contact us at: – http://www.embedded-tips.blogspot.com/ 18