SOLUTION MANUAL OF WIRELESS COMMUNICATIONS BY THEODORE S RAPPAPORT
- 1. BITS Pilani Pilani Campus Testability of VLSI Dr. Premananda B.S.
- 2. BITS Pilani Pilani Campus Testability of VLSI ESZG532/MELZG531 Lecture No. 01
- 3. BITS Pilani, Pilani Campus • Introduction • Fault Modeling and Logic Simulation • Basic Fault Simulation and Testability measures • Basics of Combinational ATPG • ATPG Algorithms • Sequential Circuit Test Generation • Delay Test Methodology and Scan based DFT • BIST-Pattern Generation and Response Compaction • Memory Test and BIST for Memory • IDDQ Tests • Boundary scan Agenda
- 4. BITS Pilani, Pilani Campus • “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI Circuits”, Michael L. Bushnell and Vishwani D. Agrawal, Kluwer Academic Publishers, 2000. • “Digital Systems Testing and Testable Design”, Miron Abromavicici, Melvi Breuer and Friedman. • “VLSI Test Principles and Architectures: Design for Testability”,Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen, Elsevier, 2006. • “Digital System Test and Testable Design: Using HDL Models and Architectures”, Zainalabedin Navabi, Springer Science & Business Media, 2010. Reference Books
- 5. BITS Pilani, Pilani Campus • Introduction to VLSI Testing • Design for Testability • VLSI Technology Trends • Types of Testing • Failure Patterns • Automated Test Equipment • Testing Economics Introduction
- 6. VLSI Testing • Once design a product, is fabricated and tested, and if it fails the test, then there must be a cause for the failure: – the test was wrong, or – the fabrication process was faulty, or – the design was incorrect, or – the specification had a problem. • Correctness and effectiveness of testing are important for quality products. • A good test process can weed out all bad products before they reach the user. • For VLSI, failing of good chips by tests is known as yield loss, which increases the cost of manufacturing.
- 7. Role of Testing • The role of testing is to detect whether something went wrong. – Detection: determination of whether or not the device under test (DUT) has some fault. • The role of diagnosis is to determine what went wrong, and where the process needs to be altered. – Diagnosis: identification of a specific fault that is present on DUT. • Device characterization: determination and correction of errors in design and/or test procedure.
- 8. Role of Testing • If the test procedure is good and the product fails, then we suspect the fabrication process, the design, or the specification. • A well-thought-out test strategy is crucial to the economical realization of products. • The benefits of testing are quality and economy. – These two attributes are not independent and neither can be defined without the other. • Quality means satisfying the user’s needs at a minimum cost.
- 9. Testing Principle How to test chips? Quality of the tested circuit will depend upon the thoroughness of the test vectors.
- 10. VLSI Realization Process Determine requirements Write specifications Design synthesis and Verification Fabrication Manufacturing test Chips to customer Customer’s need Test development
- 11. VLSI Testing • The arrows out of the FMA block represent the corrective actions applied to the faulty steps of the realization process. • Companies emphasize on doing it right the first time, or pursuing the goal of zero defects. VLSI realization process
- 12. VLSI Testing • The objective of design is to produce data necessary for the next steps of fabrication and testing. • Important function of testing is the process diagnosis. – We must find what went wrong with each faulty chip, be it in design, in fabrication, or in testing. – Or, we may have started with unrealizable specifications. • FMA uses different test types, including examination through optical and electron microscopes, to determine the failure cause and fix the process.
- 13. Failure Mode Analysis • Failures are defects that reach a customer. • Procedures for diagnosing defects and finding their causes are known as failure mode analysis. – Faulty chip analysis. • Failing devices often show patterns of repeated failures. • The causes of these failures can point to weaknesses (sensitivity to process variations) in the design. • Information is useful for improving logic and layout design rules.
- 14. A realistic VLSI realization process Digital andAnalog VLSI Testing
- 16. BITS Pilani, Pilani Campus • Introduction to VLSI Testing •Design for Testability • VLSI Technology Trends • Types of Testing • Failure Patterns • Automated Test Equipment • Testing Economics Introduction
- 17. DesignforTestability(DFT) • DFT refers to hardware design styles or added hardware that reduces test generation complexity. • Test generation complexity increases exponentially with the size of the circuit. • Example: Test hardware applies tests to blocks A and B and to the internal bus; avoids test generation for combined A and B blocks. Logic block A Logic block B PI PO Test input Test output Internal bus
- 18. Economics of DFT • Consider life-cycle cost; DFT on the chip may impact the costs at board and system levels. • Weigh costs against benefits: • Cost examples: reduced yield due to area overhead, yield loss due to non-functional tests. • Benefit examples: reduced automatic test equipment (ATE) cost due to self-test, inexpensive alternatives to the burn-in test. • A DFT or test method should be selected to improve the product quality with minimal increase in cost due to area overhead and yield loss.
- 19. Benefits and Costs of DFT Design and test + / - + / - + / - Fabri- cation + + + Manuf. Test - - - Level Chips Boards System Maintenance test - Diagnosis and repair - - Service interruption - + Cost increase - Cost saving +/- Cost increase may balance cost reduction
- 20. BITS Pilani, Pilani Campus • Introduction to VLSI Testing • Design for Testability • VLSI Technology Trends • Types of Testing • Failure Patterns • Automated Test Equipment • Testing Economics Introduction
- 21. VLSI Technology TrendsAffecting Testing • Trends have a profound effect on the cost and difficulty of chip testing. • Rising Chip Clock Rates 1. At-Speed testing 2. Automatic Test Equipment (ATE) cost 3. Electromagnetic Interference (EMI) • Increasing Transistor Density 1. Test complexity 2. Feature scaling and power dissipation 3. Current (IDDQ) testing • Integration of Analog & Digital Devices onto One Chip
- 22. Types of Testing • VLSI testing can be classified into four types depending on the specific purpose it accomplishes: 1. Characterization • Design debug or verification testing • Determines the exact limits of device operating values 2. Production • Enforce the quality requirements by determining whether the device meets the specifications 3. Burn-in • Ensures reliability of tested devices by testing, over a period of time, and by causing the bad devices to actually fail • Subjects the chips to a combination of production tests, high temperature, and over-voltage power supply 4. Incoming Inspection • To avoid placing a defective device in a system assembly
- 23. 1. Characterization • Worst-case test: – Choose a test that passes/fails chips – Select a statistically significant sample of chips – Repeat test for every combination of environmental variables – Plot results in Shmoo plot – Diagnose and correct design errors • Continue throughout the production life of chips to improve design and process to increase yield
- 24. 2. Manufacturing Test/Production • Determines whether the manufactured chip meets the specification • Must cover a high percentage of modeled faults • Must minimize test time (to control cost) • No fault diagnosis • Test every device on the chip • Test at the rated speed or at the maximum speed guaranteed by the supplier
- 25. 3. Burn-in or Stress Test • Process: – Subject chips to high temperature and over-voltage supply, while running production tests • Catches: – Infant mortality cases – these are damaged or weak (low reliability) chips that will fail in the first few days of operation – burn-in causes bad devices to fail before they are shipped to customers – Freak failures – devices having the same failure mechanisms as reliable devices
- 26. 4. Incoming Inspection • Can be: – Similar to production testing – More comprehensive than production testing – Tuned to specific system application • Often done for a random sample of devices: – Sample size depends on device quality and system reliability requirements – Avoids placing defective devices in a system where the cost of diagnosis and repair exceeds the incoming inspection cost
- 27. Types of Tests • Parametric Tests • measures electrical properties of pin electronics • DC: shorts, opens, leakage, output drive current test… • AC: delay, functional speed, access test… • fast and cheap • Functional Tests • consists of input vectors and corresponding responses • check for proper operation of a verified design by testing the internal chip nodes • cover a very high percentage of modeled faults • long and expensive
- 28. Test Specifications and Test Plan • Test Specifications: – Functional characteristics – Type of Device – Technology-CMOS, GA, standard cell… – Physical constraints – package, pin numbers, etc. – Environmental characteristics–temperature, power supply – Reliability–acceptance quality level, failure rate, etc. • Test plan generated from specifications: – Type of test equipment to use – Types of tests – Fault coverage requirement
- 29. Test Programming • Test program contains the sequence of instructions that a tester would follow to conduct testing. • An automatic test program generation (TPG) system requires three types of inputs: i. Tester specification and the information on the types of tests are obtained from the test plan. ii. Physical data on the device (pin locations, wafer map, etc.) are obtained from the layout. iii. Timing information on signals and test vectors (inputs and expected responses) are obtained from simulators.
- 31. Test Data Analysis • Test data obtained from the ATE serves three purposes: – First, it helps to accept or reject the device under test. – Second, it provides useful information about the fabrication process. – Third, it provides information about design weaknesses. • Devices that did not fail are good only if tests covered 100% of faults. • Failing tests quickly point to faulty devices. • Test data analysis allows the sorting of chips for higher than the nominal performance.
- 32. BITS Pilani, Pilani Campus • Introduction to VLSI Testing • Design for Testability • VLSI Technology Trends • Types of Testing •Failure Patterns • Automated Test Equipment • Testing Economics Introduction
- 33. Failure Pattern • A failure pattern describes how a fault becomes a failure indicating how the fault propagates through the system units until it produces a failure. • The pattern explicitly shows how flaws in the system allow the propagation of faults. • The information in failure patterns is useful to evaluate and design reliable systems.
- 34. Types of Failures Failures can be: • Manufacturing failures – Defect or outside parametric specifications • Functional failures – Chip fails under all conditions • Electrical failures – Malfunctions under certain conditions – Shmoo plots can help to debug electrical failures in silicon
- 35. Shmoo Plots • The Shmoo plot is plotted as: – voltage on the X-axis – speed on the Y-axis • A healthy normal chip should operate at increasing frequency as the voltages increase. • Normal shmoo plot should show speed increasing as temperature decreases. • The brick wall pattern suggests that the chip may be randomly initialized in one of the two states, only one of which is correct.
- 36. Shmoo Plots
- 37. Shmoo Plots • Failures at low temperatures could indicate coupling or charge-sharing noise exacerbated by faster edge rates. • Failures at high temperatures could indicate excessive leakage or noise problems exacerbated by the lower threshold voltages. • Walls at either temperature indicate race conditions where the path that wins the race varies with temperature.
- 38. Shmoo Plots • In the floor, leakage problem where the part fails at a low frequency independent of the voltage. • A finger indicates coupling problems dependent on the alignment, where at certain frequencies the alignment always causes a failure.
- 39. • At1.8Vthechipworksforclockperiodsof2.3nsandgreater. Athighervoltages,thechipcanoperateatshorterperiods. Alpha 21164 Shmoo Plot
- 40. How to diagnose failures? • Hard to access chips • Pico probes • Electron beam • Laser voltage probing • Picosecond imaging circuit analysis • Infrared imaging • Focused ion beam
- 41. BITS Pilani, Pilani Campus • Introduction to VLSI Testing • Design for Testability • VLSI Technology Trends • Types of Testing • Failure Patterns • Automated Test Equipment • Testing Economics Introduction
- 42. Automatic Test Equipment (ATE) • The ATE is an instrument used to apply test patterns to a DUT/CUT, analyze the responses from the DUT, and mark the DUT as good or bad. • The ATE is controlled by a central UNIX work station or PC, and additional CPUs is often built into it to provide data reduction capability. • The tester has one or more test heads. • The ATE is connected to external equipment that handles the wafers or IC packages being tested. – While one chip or wafer is being tested in one test head (chip handler), another chip/wafer can be loaded into a second test head, so the tester overlaps mechanical handling of parts with electrical testing of parts.
- 43. Automatic Test Equipment • ATE Consists of: – Powerful computer – Powerful 32-bit Digital Signal Processor (DSP) for analog testing – Test Program (written in a high-level language) running on the computer – Probe Head (actually touches the bare or packaged chip to perform fault detection experiments) – Probe Card (contains electronics to measure signals on chip pin or pad)
- 45. T6682ATE Specifications • Uses 0.35μ VLSI chips in implementation • 1,024 digital pin channels • Speed: 250, 500, or 1000 MHz • Timing accuracy: +/- 200 ps • Drive voltage: - 2.5 to 6 V • Clock/strobe accuracy: +/- 870 ps • Clock settling resolution: 31.25 ps • Pattern multiplexing: write 2 patterns in one ATE cycle • Pin multiplexing: use 2 pins to control 1 DUT pin
- 46. Block Diagram of T6682 VLSI Test System
- 47. T6682 ATE Software • Runs Solaris UNIX on UltraSPARC 167 MHz CPU for non-real-time functions. • Runs real-time OS on UltraSPARC 200 MHz CPU for tester control. • Peripherals: disk, CD-ROM, micro-floppy, monitor, keyboard, HP GPIB, Ethernet. • Viewpoint software provided to debug, evaluate, and analyze VLSI chips.
- 48. Test Description Language (TDL) • A test programming language, used to describe a program that operates the ATE using the test vectors. • Provides this information for controlling the ATE: – strobe times (for sampling the DUT outputs), voltage/current stimulus information, the clocking rate for vectors, the vector slew rate (rate at which waveforms rise or fall), and filtering information for sampling DUT signals. • In TDL one can set the resolution of the pin signal, which is useful for determining causes of failures in DUTs. • Test vectors must be edited, to adjust them to avoid burning out the chip by exceeding the maximum allowable power dissipation.
- 49. Multi-site Testing • One ATE tests several devices at the same time • For both probe and package test • DUT interface board has > 1 sockets • Add more instruments to ATE to handle multiple devices simultaneously • Usually test 2 or 4 DUTs at a time, usually test 32 or 64 memory chips at a time • Major cost reduction • Limits: number of instruments available in ATE, type of handling equipment available for package
- 50. BITS Pilani, Pilani Campus • Introduction to VLSI Testing • Design for Testability • VLSI Technology Trends • Types of Testing • Failure Patterns • Automated Test Equipment •Testing Economics Introduction
- 51. Costs of Testing • Design for testability (DFT) – Chip area overhead and yield reduction – Performance overhead • Software processes of test – Test generation and fault simulation – Test programming and debugging • Manufacturing test – Automatic test equipment (ATE) capital cost – Test center operational cost
- 52. Costs • Costs include the: – cost of DFT – cost of ATE (initial and running costs) – cost of test development (CAD tools, test programming, test vector generation…) • In future, DFT will dominate test economics equations. • The scan design technique can significantly reduce the cost of test generation. • BIST method can lower the complexity and cost of ATE. • DFT techniques should, be included in the device specification and the test plan.
- 53. The Rule of Ten • Chips must be tested before they are assembled onto printed circuit boards (PCBs), which, in turn, must be tested before they are assembled into systems. • Experience has shown that the rule of ten holds. • If a chip fault is not caught by chip testing, then finding the fault costs *10 times as much at the PCB level as at the chip level. • Similarly, if a board fault is not caught by PCB testing, then finding the fault costs *10 times as much at the system level as at the board level.
- 54. VLSI Chip Yield • A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. • A chip with no manufacturing defect is called a good chip. • The fraction (or percentage) of good chips produced in a manufacturing process is called the yield. • The term wafer yield is sometimes used to refer to the average number of good chips produced per wafer. • Testing cannot improve the process yield. • There are two ways of improving the process yield: i. Diagnosis and repair ii. Process diagnosis and correction
- 55. Clustered VLSI Defects Wafer Defects Faulty chips Good chips Unclustered defects Wafer yield = 12/22 = 0.55 Clustered defects (VLSI) Wafer yield = 17/22 = 0.77
- 56. Yield Equation Y = Prob ( zero defect on a chip ) = p (0) Y = ( 1 + Ad / α ) – α A: Area of a chip d: Defect density α: clustering parameter Example: Ad = 1.0, α = 0.5, then, Y = 0.58 Unclustered defects: α = ∞, Y = e - Ad Example: Ad = 1.0, α = ∞, then, Y = 0.37
- 57. Defect Level or Reject Ratio • Defect level (DL) is the ratio of faulty chips among the chips that pass tests, measured as parts per million (ppm). • A measure of the effectiveness of tests. • A quantitative measure of the manufactured product quality. • The DL is determined from the field return data. • The chips thus returned are examined by the manufacturer to determine the causes of failures. • These causes may point to areas of improvement in specification, design, fabrication, or test. • Such improvements reduce the defect level. • For VLSI chips, while a defect level of 500 ppm may be acceptable, 100 ppm or lower represents high quality.
- 58. Summary • Overall benefit/cost ratio for design, test, and manufacturing should be maximized; one should select the most economical design over the cheapest design. • A DFT or test method should be selected to improve the product quality with minimal increase in cost due to area overhead and yield loss. • VLSI yield depends on two process parameters, defect density (d) and clustering parameter (α). • Yield drops as chip area increases; low yield means high cost. • Fault coverage measures the test quality. • Defect level (DL) or reject ratio is a measure of chip quality. • DL can be determined by an analysis of test data.
- 59. Summary • Parametric tests – determine whether the pin electronics system meets digital logic voltage, current, and delay time specs • Functional tests – determine whether internal logic/analog sub-systems behave correctly • ATE Cost Problems – Pin inductance (expensive probing) – Multi-GHz frequencies – High pin count (1024) • ATE Cost Reduction – Multi-Site Testing – DFT methods like Built-In Self-Test
- 60. BITS Pilani, Pilani Campus THANK YOU
- 61. Pattern Generation • Sequential pattern generator (SQPG): stores 16M vectors of patterns to apply to DUT -- vector width determined by # DUT pins • Algorithmic pattern generator (ALPG): 32 independent address bits, 36 data bits – For memory test – has address descrambler – Has address failure memory • Scan pattern generator (SCPG) supports JTAG boundary scan, greatly reduces test vector memory for full-scan testing
- 62. Response Checking and Frame Processor • Response Checking: – Pulse train matching – ATE matches patterns on 1 pin for up to 16 cycles – Pattern matching mode – matches pattern on a number of pins in 1 cycle – Determines whether DUT output is correct, changes patterns in real time • Frame Processor – combines DUT input stimulus from pattern generators with DUT output waveform comparison • Strobe time – interval after pattern application when outputs sampled
- 63. Probing • The digital pin electronics is the local buffering circuitry, which is placed as close as possible to the DUT in order to provide maximum bandwidth and minimum parasitic. • Each pin (channel) on the Advantest ATE has one comparator (DUT output-only) pin and a conventional driver/comparator pin. • The pin electronics terminates in a pogo pin connector at the test head. • The test head is interfaced through a custom PCB to a wafer prober for the testing of uncut and unpackaged wafers or to a package handler for the testing of packaged chips through a testing socket.
- 64. Verification vs. Test • Verifies correctness of design. • Performed by simulation, hardware emulation, or formal methods. • Performed once prior to manufacturing. • Responsible for quality of design. • Verifies correctness of manufactured hardware. • Two-part process: – Test generation: software process executed once during design – Test application: electrical tests applied to hardware • Test application performed on every manufactured device. • Responsible for quality of devices.