SOTA.pptx

URSI Regional Conference on Radio Science (URSI RCRS 2020)
Investigation of Heterojunction Silicon-on-Insulator Tunnel field Effect
Transistor in Nanometer Era
PRESENTED BY
ASHISH KUMAR SINGH
PHD RESEARCH SCHOLAR
DEPARTMENT OF ELECTRONICS ENGINEERING
INDIAN INSTITUTE OF TECHNOLOGY
(BHU),VARANASI, INDIA
7/30/2022 1

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 Introduction
 Basic Structure and Operating Principle of TFET
 History and State-of-the-Art
 Investigation of Ge-source/Si Strained SOI TFET
 Proposed Ge-Source SOI TFET with Oxide Overlap
 2D Analytical Model of the Proposed Device
 2D Analytical Gate Threshold Voltage Model of the Proposed Device
 Conclusions and Future work
 Publications
 References
OUTLINE

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Chapter 1: Introduction
Chapter 2: History and State-of-the -Art
Chapter 3: TFET: Basic Structure and Operation Principle
Chapter 4: Investigation of Ge-source/Si Strained SOI TFET
Chapter 5: Proposed Ge-Source SOI TFET with Oxide Overlap
Chapter 6: 2D Analytical Model of the Proposed Device
Chapter 7: 2D Analytical Gate Threshold Voltage Model of the Proposed Device
Chapter 8: Conclusions and Future work
Organization of the Thesis

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 Subthreshold Leakage Current.
 Short channel Effects.
 Gate Tunneling Currents.
 Time Dependent Dielectric Breakdown.
Limitation of MOSFET

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New ideas, technologies, concepts and alternative devices will be required for continued
performance improvements.
Scaling: Tunneling field effect transistor (TFET) designs do not suffer from short channel
effects
Power Dissipation: TFETs can beat the 60 mV/decade sub-threshold swing of MOSFETs
Design Flexibility: Circuits can be made with fewer devices.
Introduction

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 In nanometer regime, the technology is facing many critical challenges and reliability
issues.
 Aggressive scaling of MOSFET has resulted in short channel effects and exponential rise
in leakage current.
 To mitigate these issues, Tunnel FET is extensively studied. This is considered to be the
most promising devices for possible applications in future VLSI.
Introduction

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In nanometer regime, the technology is facing many critical challenges and
reliability issues.
Aggressive scaling of MOSFET has resulted in short channel effects and
exponential rise in leakage current.
To mitigate these issues, Carbon nanotubes and Nanowire–FETs are
extensively studied.
These are considered to be the most promising devices for possible
applications in future VLSI.

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MOSFET vs. TFET
MOSFET:
• Classical device
• High ION
• SS > 60mV/dec
TFET:
• Quantum device
• Extremely Low IOFF
• SS < 60mV/dec
• Low ION
MOSFET
TFET

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 TFET can allow lower sub-threshold swing for lower operating voltages.
 High Ion/Ioff ratio ( > 107).
 Fabrication of TFET compared to other alternative devices is compatible with standard CMOS
processing since it can be implemented as a reverse biased gate p-i-n diode.
 Leads to chips that consume less power.
 Negative differential resistance (NDR) properties can be exploited to create simpler designs.
Chapter-1
Introduction

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Tunnel FET : Basic Device Operation
P-type TFET
N-type TFET

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 Tunneling is a quantum mechanical phenomenon with no analog in classical physics.
 It occurs when an electron passes through a potential barrier without having enough
energy to do so.
 The mathematical formulations of quantum tunneling is Schrödinger formulations
presents an interesting phenomenon where a particle tunnels through an energy
barrier.
 Band-to band tunneling is the quantum mechanical phenomena in which the electrons
“tunnel” across the energy gap of the semiconductor.
 For direct tunneling , an electrons travels from the valance band to the conduction band
without the absorption or emission of phonon.
 In the indirect tunneling process, the tunneling particle acquires by change in
momentum by absorbing and emitting the phonon.
Quantum Tunneling

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Chapter-2
 Semiconductor industry is looking for different materials and devices to integrate with
the current silicon based technology in a long term future.
 Tunnel FET is found to be the most promising candidate in this context.
 Much progress has been made in recent years showing that TFETs can outperform the
state of the art silicon FETs in many ways.
History and State-of-the-art

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 The key point of this device is that the gate overlapping with the source is essential to make surface inversion.
 Oxide thickness used are 15nm and 20nm; Doping varies from 1E17/cm3 to 1E19/cm3 .
 If doping is higher 1E19/cm3, the surface electric fields are high and most of the voltage drop across oxide and there is less band gap of band bending in Si.
 If the doping density is lower 1E17/cm3 although the band bending is large, the depletion regions are too wide to allow significant tunneling.
 If the doping density is 1E18/cm3 then there is onset of current at Vg= Vd = 3 V with oxide thickness 15 nm.
 If the oxide thickness will increase the tunnel current decreases because the electric field in the Silicon at the same voltage will decrease.
In 1987, Banerjee et al. at Texas Instruments studied the behavior of a three-terminal silicon tunnel device using a p- -region instead of an intrinsic region under
the gate.
Banerjee et al. in 1987

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First experiment al demonstration of three terminal TFET with Ion=10-6uA/um @VGS=-5V.
Tunneling barrier is formed when a negative bias is applied to the gate creating an accumulation layer underneath the oxide.
The device has the potential for much improved performance over existing transistors because of the tunneling nature.
Reddick and Amaratunga at Cambridge reported experiments on silicon surface tunnel transistors.. They were motivated by the desire for devices that would be
faster than conventional MOSFETs, as tunneling devices are, and that could be scaled down more easily without running into problems such as punchthrough.
Reddick et al. in 1995

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They fabricated a Si vertical TFET to also gate the Zener side of the tunnel junction and noted its potential for low off-current relative to the MOSFET.
 n+ is source and p+ is drain and Pt and Ti/W is gate.
Threshold Voltage is almost 3 mV.
.
Hansch et al. in 2000

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 Optimization of electrical parameters of a vertical TFET
 SiGe replaced the silicon delta layer already used by Hansch, and in theory, the smaller
bandgap should have reduced the tunnel barrier width and increased tunneling current in the
on-state as well as lowering the subthreshold swing.
 Effect of mole fraction in subthreshold swing
 δp Si is replaced by δp SiGe
 With SiGe, the tunneling currents increases with increasing x, and therefore Vt is lower
significantly.
Bhuwalka et al. in 2004

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 Studied the scaling properties of TEFT device for 130 nm,90 nm and 65 nm node.
 For 130 nm node the Vt is very high and causes the degradation of the ON current at supply voltage
of 1.5 V.
 For 90 nm node, the ON current is improved by factor of 10 ,Vt reduced, subthreshold swing of 75
mV/decade and DIBL is only 60mV which is comparable to the MOSFET..
 For 65 nm node, the ON current is improved by factor of 10 ,Vt reduced more ,subthreshold swing of
78 mV/decade ,DIBL is only 15mV and OFF current is 14 pA/um.
.
Nirschl et al. in 2006

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 S & D doped with 1020 cm-3 and the p-type body doped with 1017 cm-3, L = 50 nm,
tdielectric = 3 nm, and tSi = 5 nm. Vd = 1 V.
 Using a high-κ gate dielectric showing an ON-current as high as 0.23 mA for a gate voltage
of 1.8 V, an OFF-current of less than 1 fA, an improved average subthreshold swing of 57
mV/dec, and a minimum point slope of 11 mV/dec.
 As temperature increases, Ioff increases, but Ion changes very little. Slopes are only
slightly affected by changes in temperature.
 On current increases and decreases the subthreshold swing as the gate dielectric constant
increases.
K. Boucart in 2007

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 Threshold voltage is 0.12 V.
 Ion 12.1 μA / μm and 5.4 nA / μm
 Subthreshold swing depends upon oxide thickness and SOI layer thickness.
 The use of lower EOT ,lower bandgap material and more abrupt source doping profile will increase
ON current .
High-k material can be used.
Choi et al. in 2007

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 Ion = 300uA/um and SS~50mV/decade
 Reduce the amipolarity by using the hetrostructure of large bandgap material at the drain side to reduce the tunneling.
.
Krishnamohan et al. in 2008

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 First experitmental investigation on SOI,GeOI and Si1-x Gex TFET.
 Introducing a novel TFET architecture to solve the ambipolar nature called
the DFET( Drift TFET) by increasing the OFF current.
 Small bandgap material is used to increase the ON current.
 Intrinsic area Si is responsible for reducing ambipolarity.
 SiN is used as protection layer to avoid the undesired silicidation of the
area.
Mayer et al. in 2008

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 Ge in the source of an n-channel TFET, record high ION/IOFF
ratio (>106) is achieved for low-voltage (0.5V) operation.
 ION(μA/μm) = 0.42
 IOFF(pA/μm) = 0.12
 ION/IOFF = 3E6
 Not discussed about subthreshold swing.
Kim et al., in 2009

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 This paper study the sensitivity to parameter fluctuations for an optimized double-gate silicon Tunnel FET with a high-k
gate dielectric.
Boucart et al., in 2010

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.
Boucart et al., in 2010

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 Steepest SS (<60mV/decade) ever reported in a III-V TFET
 Heterojunction TFET shows steeper SS over a wider range of ID than the homojunction
TFET.
 Electrical oxide thickness (EOT) scaling and increased source doping in tandem with
tunnel barrier height reduction are shown to greatly improve the SS of the III-V TFETs
and increase ID by more than 20X.
Dewey et al., in 2011

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 ION enhancements over n-channel
In0:53Ga0:47As Homj-TFET are
experimentally demonstrated by
utilizing i) a staggered GaAs0:5Sb0:5
source and ii) an N+ pocket (δ)-doped
channel.
 Hetj-TFET showing the maximum ION of
60 μA/μm at VGS = 2.5 V. at VDS = 0.75 V.
Mohata et al., in 2011

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 Ion reaches ∼140 μA/μm at Vgs = 1.2 V and Vds = 0.5 V for a Ge content of 50%.
 SS is less than 60 mV/dec for a very large Id range.
 With increasing Ge content, the on-current increases due to the reduced band-
gap energy.
The key steps include very thin Si layer growth, steep doping in the SiGe layer,
and selective etch of the SiGe layer.
Zhao et al., in 2011

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P-type Be-doped (NA = ~5×1016 cm-3) In0.53Ga0.47
 Gallium doped P+ Ge-source .
Gate stack comprising 5.6-nm Al2O3 and 120-nm TaN was formed.
.
Guo et al., in 2012

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.
Chang et al., in 2012
 SS is 46 mV/dec at 1 pA/μm
 ION/IOFF ratio is 1.4×107
 ION is 1.4 μA/μm
 IOFF is 0.1 pA/μm

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 epi-Ge HTFET shows the subthreshold swing from 120–240 mV/dec with IDS = 10−11–
10−10 A/μm, which is smaller than Si TFET.
 epi-Ge device shows drain current as high as 11 μA/μm at VGS = VDS = −2 V, which
enhances 2.3 times as compared with that of Si HTFET.
Lee et al., in 2013

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 By lowering the supply voltage below 0.5 V, up to 10× reduction of the energy delay product is
feasible by using area tunneling devices.
 Different VT is achieved by varying doping concentration in epitaxial layer.
.
Rajoriya et al. in 2013

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 High Subthreshold Swing
 Low on current
 High threshold voltage
 High Miller capacitance
 Lack of Modeling of Tunnel FET
Major Limitations of the TFET

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Chapter 4
Investigation of Ge-source/strained Si SOI-TFET

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Tunneling Models
37.1
69.2
85.3
102.1
0
20
40
60
80
100
120
Subthreshold
Swing
Different Models

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 
I vs. characteristics for different channel length L .
DS GS
V  
I vs. characteristics for different oxide thickness .
DS GS ox
V t

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I vs. characteristics for different dielectric materials.
DS GS
V I vs. characteristics for different doping
levels of homo and hetero junction SOI-TFET.
DS GS
V

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I vs. characteristicsfor different overlaps
of proposed homo and hetero junction SOI-TFET.
DS GS
V DS GS
I vs. V characteristicsfor different overlaps for different
overlaps/underlaps of proposed hetero junction SOI TFET

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Impact of Ge-concentration
. characteristics for different Ge concentration.
DS GS
I vs V . characteristics for different Ge concentration.
DS DS
I vs V

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. characteristics for different Ge concentration.
C vs V
 
a  
b
 
c  
d
 
   
Impact of Ge concentration on (a) /I ratio b
c d V using CC and TC method.
ON OFF m
out t
I g
R

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Chapter 5
Proposed Ge-source SOI-TFET with Oxide Overlap
Cross sectional view conventional
of proposed Ge-source SOI-TFET.
Cross sectional view of gate overlap
on Ge-source of propose SOI-TFET.
Cross sectional view of oxide overlap
on Ge-source of propose SOI-TFET.

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Energy band along the channel for conventional TFET,
oxide overlap and gate overlap of the proposed device.

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. and . characteristic for conventional TFET, oxide overlap and gate overlap
of the proposed device
DS GS DS DS
I vs V I vs V

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Normalized - characteristics and - characteristics for conventional TFET, oxide overlap and
gate overlap of the proposed device.
gd DS
C V C V

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Proposed Ge-Source SOI TFET with Oxide Overlap
. for different dielectric materials.
DS GS
I vs V
. for different V
DS GS DS
I vs V

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 
     
 
Drain voltage variation for the a Point and Average Subthreshold Swing
b Threshold volta Transconductance
ge using CC and TC method c
d / ratio of the proposed device.
m
ON OFF
g
I I
 
a  
c
 
b
 
d

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Process Flow of the Proposed Device
   
 
2 2
a SOI wafer b gate stack consisting of AlN/ HfO , Aluminum, LTO gate-hardmask and HfO gate-sidewall
spacers on source were deposited and patterned c drain region is implanted with As+ and the source regio
 
n etche-
disotropically to form oxide-to-source overlap area d Ge is selectively deposited only.
 
a  
b  
c  
d

References
VDD(V)
Gate
Length
(µm)
ION
(µA/um)
IOFF
(pA/um)
ION/IOFF
SS@
(1nA/µm)
(mV/dec)
Steepest SS
(mV/dec)
EOT
(nm)
Body Structure
W.M. Reddick
et al.[5]
5 3µm 0.01 0.1 105 >600 >600 24 Bulk Si
P.F. Wang
et al. [17] 3 100 nm 0.02 10 2x103 450 375 6 Bulk Si
W.Y. Choi
et al. [18]
1 70nm 12.1 1000 1.2x104 60 52.8 2
SOI
TSi= 70 nm
F. Mayer
et.al [19]
1 0.02 1 2x104 330 42 3
(HFO2)
SOI
TSi = 20 nm
S.H. Kim
et al. [20] 0.5 0.25-5µm 0.42 0.14 3x106 80 40 3
SOI
TSi = 70 nm
(poly- Ge source)
K. Jeon
et al.[21] 1 20µm 1.2 0.017 7x107 70 46 0.9
(HFO2)
SOI
Tsi = 40 nm
(source Ni-Silicate + pocket formation)
R. Gandhi
et al.[22] 1.2 GAA 0.02
0.2
105 1000 50 4.5 Silicon NW diameter = 40 nm
(GAA structure)
Hsu-Yu Chang et al.[30]
1.1 100nm 1.4 0.1 1.4×107 77 46 3.5
(Al2O3)
SOI
TSi = 50nm
(with dopant pocket)
Our Work
0.5
30nm
33 8.55 3.4×109 44 37 1.4
(HfO2/SiO2)
SGOI
TSiGe = 20nm
(with germanium as source)
7/30/2022 47

7/30/2022 48
Chapter 6
Analytical Modeling of the Heterojunction SOI TFET with Oxide Overlap
Cross sectional view of the proposed device
For subthreshold region of operations, it is assumed that:
No mobile charges in the channel and no depletion region at
source/drain channel interfaces.
Doping profiles of source/drain channe

 l junctions are abrupt.
Thick buried oxide is used , hence, the vertical electric field in
the channel/buried oxide interface is assumed to be negligible.


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characteristics of the proposed d
- evice.
DS GS
I V characteristics of the proposed d
- evice.
DS DS
I V
Simulation Results

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Surface Potential
The potential distribution in the channel is governed by 2D Poisson’s equation and is given by:
   
2 2
2 2
, ,
where, is the electrostat
0
ic potential.
x y x y
x y
 

 
 
 
 
           
 
 
To solve , potential is divided into two parts:
,
, , , ,
where, is the solution of 1D Poisson's equation,
, is th ol
e s
L R
x y
x y V y U x y V y U x y U x y
V y
U x y

     
ution of 2D Poisson's equation.

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Surface Potential
The potential distribution in the channel is governed by 2D Poisson’s equation and is given by:
   
2 2
2 2
, ,
where, is the electrostat
0
ic potential.
x y x y
x y
 

 
 
 
 
, is divided into U and U
L R
U x y
       
   
, , ,
where, is the solution of 1D Poisson's equation, , is the
To solve , potential is divided i
solution of 2D Poisson's equation.
nto two parts:
x y x y V y U x y
V y U x y
   
 
To solve the field discontinuity at germanium/oxide and silicon/oxide interface the physical gate oxide
thickness is converted into: and for Si and Ge regions, respect
ge si
ox ox ox ox ox
ox ox
t t t t
t
 
 

 
 ively.
where , , and are the relative permittivities of the oxide, silicon, and germanium, respectively, and
is the physical thickness of the gate oxide stack
  
ox si ge
ox
t

7/30/2022 52
 
 
1D solution of Poisson's equation
is given by:
G
G
V y
V y y
W


 
Surface Potential
 
 
       
       
 
 
The necessary boundary conditions are:
,0 0
( , )
, 0 0
0, 0,
, ,
0,
,
y W
S
D DS
S G
S
D G
D
U x
dW x y
U x W
dx
U y y y V y
U L y L y y V V y
y y
t
L y y
t
  
  
 
 
 
 


  
   
    

 

 
where,
for the overlap region
for the channel region
the thickness of the silicon body
,
=
=
=gate voltag
flat band voltage
e
G F
si ox
si ox
si
G
G
F
S B
B
S
W
V
V
W t t
t t
t
V
V


 

 

 
Here, is for overlap region and is for channel
region, and are the built-in potentials at source/drain
channel junction, respectively, is drain-to-source voltage.
ox ox
S D
DS
t t t t
V
 
 
 

7/30/2022 53
2 2
2 2
For 2D analysis, let us consider
( , ) ( , )
0
 
 
 
U x y U x y
x y
 
 
Using separation of variable method is used to solve , and is given as:
, ( ) ( )

U x y
U x y X x Y y
 
 
   
0
2D solution of the Poisson's equation using suitable boundary conditions is given by:
sinh sinh
, sin sin
sinh sinh
 
 
 


 

 
 
 
 
 

n n n n
n n
n n
n
A L x B x
U x y y y
L L
   
2
here
1 2
w
 
 
n n W
Surface Potential

7/30/2022 54
 
 
 
 
 
 
Solving the constants and , the values are given as:
sin sin
2
cos
sin sin
2
cos
n n
ox
S GS GS
n S
ox
D GS GS
n D
A B
rt W
V V
A W
W t W
rt W
V V
B W
W t W
 

 
  
 

 
  
 

  
 
 
 

  
 
 
   
   
0
0
The constants and are given as:
2
0, sin
2
, sin
n n
W
n n
W
n n
A B
A U y y dy
W
B U L y y dy
W






 
Variation of the constants with number of terms n .
Parameters A and
n n
B

7/30/2022 55
 
 
 
 
 
 
 
0 0
Using 1D and 2D solution , we can get the electrostatic potential
sinh sinh
( , ) sin sin
sinh sinh
n n n n
GS
GS n n
n n
n n
A L x B x
V
x y V y y y
W L L
 
  
 
 
 
   

   
   
   
 
   
 
 
 
 
 
 
 
surface
0 0
The surface potential is given as:
sinh sinh
sin sin 1
sinh sinh
n n ox
ox ox GS
n n
A L x B x rt
rt rt V
L L W
 
  
 
 
 
 
  
   
 
 
 
 
 
 

7/30/2022 56
.
variation along the channel for different V .
s GS
 variation along the channel for different L.
s

Model Verification

7/30/2022 57
Electric Field and Band Gap
The horizontal and vertical electric-field distribution can be obtained by differentiating the potential function in,
and are given by:
   
 
 
 
 
 
 
   
 
 
 
 
 
 
0 0
0 0
sin sin
,
cosh cosh
sinh sinh
sinh sinh
,
cos cos
sinh sinh
n n
x n n n n n n
n n
n n
n n
G
y n n n n n n
n n
n n
y y
x y
E A L x B x
x L L
L x x
x y
E A y B y
y W L L
 

   
 
 
 
   
 
 
 
 
 

    



    

 
 
2 2
The absolute electric field is expressed as :  
x y
E E E
The conduction bandand valance bandare defined as:
 
 
  
   
C
V g
E q
E E q
where, is the electrostatic potential, is the electron affinity and is the effective energy band g .
ap

 g
E

7/30/2022 58
.
Energy band diagram along the channel for different V .
GS
Electric Field variation along the channel.
Model Verification

7/30/2022 59
Drain Current
 
,
DS
I q G x y dxdy
 
 
Based on the model expressions, of the device is calculated numerically using the integration of the on
BTBT Generation rate G of the dev e:
ic
DS
I
2
exp
B
G AE
E

 
  
 
 
1 2
2
1 2 2
3 2
2 1 2
: 9 (300 )
For direct tunneling pr
(300
o
)
cess r o g C
r g C
A g m qF h E K
B m E K qh


 
  
 
 
  
 
 
Kane nonlocal electric field is used for the calculation of BTBT direct generation rate G , and is given by:
1 , is the elementary charge, is the conduction band offset,
is the degeneracy factor, is Planck's c
where, is the elec
onstant and is reduced tunneling mass.
tric field, o C
r
F V cm q
g h m
E  
18 1 1 2 7
18 1 1 2 7
For TCAD simulation A and B are
For analytical model A a
9.16 10 and 3.1 10 / .
8.1 10 and 2.95 10 / .
nd B are
  
  
 
 
cm s V V cm
cm s V V cm

7/30/2022 60
Transfer characteristics of the SOI -TFET
device for different dielectric materials.
Simulated - characteristics for hetero
and homo junction of the proposed de e
vic .
DS GS
I V
Model Verification

7/30/2022 61
Cross-sectional schematic of the proposed
n-type SOI-TFET.
Chapter 7
2D Gate Threshold Voltage Model of the Ge-source SOI TFET with Oxide/Source
Overlap

62
Gate threshold voltage model
where is the gap energy and is the applied reverse bias at the source.
g S
E V
 
 
   
 
The depletion region length at the source-body
junction is given by
2
1 2
ge S
A A si ge si D
V y
l
qN N N
 
  


 
In TFET, the gate threshold volatge is the applied gate
voltage at which the energy barrier starts to saturate.
This effective inflection point in tunneling barrier width
at the tunneling junction is given by:
( )
g
bw
S S
E l
T
q V




Cont…
When the potential at reaches, the drain current becomes a linear
function of the gate voltage and the corresponding which is found by solving
the following equation:
bw DS D
gs t
x T V
V V

 

 
 
 
 
 
0
0
sinh
sin
sinh
sinh
sin 1
sinh
n bw
ox
n
DS D
n bw ox
ox GS
n
A L T
rt
L
V
B T rt
rt V
L W











 
 

 
 
 
 
 
 
   
 
 
   
  
   
 
 
 
 
 


Due to the hyperbolic terms the above equation cannot be solved for in closed f m
or .
gs
V
   
 
   
   
0
sin
2
cos sin
For a long-ch
sin sin
2
annel device , the threshold voltage can be a
1 sin
pproximated by:
tL
ox
DS D S ox
ox
n
tL
ox
ox
ox
L V
rt
V W rt
W rt
V
rt W
t
W W rt W

   
 
 
  


 
 
  
 
 

 
  
 
 

 
0
ox
n
rt




64

Cont…
 
  1 2 3
Expanding the hyperbolic terms around using Taylor’s series
and retaining only the first two
sinh
s
terms, we
inh
get
gs tL
bw gs
V V
L T B B B V



   
  1 2 3
bw gs
T A A A V
  
 
 
   
  
   
 
      
   
 
1
2
3 2
1 2
3
where, sinh ,
0.5 cosh ,
0.5 cosh ,
sinh , 0.5 cosh ,
0.5 cosh and
2 1
1
tL
tL tL FB tL
tL tL gs
tL tL tL FB tL
tL tL gs
g ge ox ox
S A
B L K V
B K V L K V V V
B B K V L K V V
A K V A K V K V V V
A K V K V V
E t W rt
K
qN W

 
 
  
 


 
  
  
  

  
 
 
 
65

Cont…
    
 
 
 
 
 
 
 
 
 
2
3 3 1
0
3 3 2
3 3 2 1 1
0
1 2 2
1 2
0
4
2
where,
2sin sinh
2sin
1
sinh
2sin
sinh
gs t
ox
n
D
ox
ox
FB
n
S D
ox
n
b b ac
V V
a
a t B A C W L
A B C
t
rt
b
W W L A B V K K C
K K C
t
c
W L K K V
  
 

 
 

 






  
 
 
 

 
 
    
 
   
   
 


 


  
1
1 1 2 2 1 2
1
; and .
ox
FB DS D
FB
rt
V V
W
C
K B B K A A

 
   
   
   
 
 
 
   
66

Cont…
The expressionfor is the approximation of Taylor series expansion which is
valid for The model calculation become accurate when the deviation of the
threshold voltage from its long channel counterpart
 
fulfills this condition. A
thicker high-K dielectric gives rise to larger effective oxide thickness EOT ,
which makes larger. For such cases, the actual threshold voltage for smaller
channel length may differ significantly fromand the model will fail to predict
accurate results.
67

7/30/2022 68
variation along the channel for different V .
surface GS
 of propos
vs. V ed device.
t DS
V
Model Verification

7/30/2022 69
for different dielectric materials of
proposed Si-based homojunction devic
.
e
vs
.
t
V L for different dielectric materials of
proposed heterojunction device with Ge-source
vs
.
.
t
V L
Model Verification

7/30/2022 70
of propose
vs. d device.
t ox
V t
Model Verification

7/30/2022 75
 Today TFETs represent the most promising steep-slope switch candidate, having the potential to use a supply voltage
significantly below 0.5 V and thereby offering significant power dissipation savings. Because of their low off currents,
they are ideally suited for low-power and low-standby-power logic applications operating at moderate frequencies.
 The biggest challenge is to achieve high performance (high ION) without degrading IOFF, combined with an S of less
than 60 mV per decade over more than four decades of drain current. This requires the additive combination of the
many technology boosters which are available or under research.
Conclusion

7/30/2022 76
 Today TFETs represent the most promising steep-slope switch candidate, having the potential to use a supply voltage
significantly below 0.5 V and thereby offering significant power dissipation savings. Because of their low off currents,
they are ideally suited for low-power and low-standby-power logic applications operating at moderate frequencies.
 The biggest challenge is to achieve high performance (high ION) without degrading IOFF, combined with an S of less
than 60 mV per decade over more than four decades of drain current. This requires the additive combination of the
many technology boosters which are available or under research.
Future Work

30 July 2022 77
Journal:
1. Sweta Chander and S. Baishya, “Hetero-Junction SOI-Tunnel FET with Oxide/Source Overlap,” Elsevier Superlattices &
Microstructures, Revised, Version Under Review (SCI: impact factor 2.09).
2. Sweta Chander and S. Baishya, “Hetero-Junction SOI-Tunnel FET with Oxide/Source Overlap,” Elsevier Superlattices &
Microstructures, vol. 85, pp. 45-50, July 2015 (SCI: impact factor 2.09).
3. Sweta Chander and S. Baishya, “A Two-dimensional Gate Threshold Voltage Model for a Hetero- Junction SOI-Tunnel FET with
Oxide/Source Overlap”, IEEE Electron Device Letters, vol. 36, no. 7, pp. 714-716, May 2015 (SCI: impact factor 2.77).
Publications
Conference:
1. Accepted, Sweta Chander and S. Baishya, “Study of Heterostructure Silicon-on-Insulator Tunnel FET,” 12th IEEE India International
conference (INDICON 2015), Jamia Milia Islamia, New Delhi, India, December 17-20, 2015,.
2. Accepted, Sweta Chander and S. Baishya, “Nanoscale Characterization of Heterostructure SOI Tunnel FET,” 4th International
Conference on Advanced Nanomaterials and Nanotechnology (ICANN 2015), IIT Guwahati, India, December 8-11, 2015.
3. Accepted, Sweta Chander and S. Baishya, “Improved Miller Capacitance of New Heterostructure Silicon-on-Insulator Tunnel FET,”
IEEE International Conference TENCON 2015, Macau, China, November 1-4, 2015.
4. Sweta Chander and S. Baishya, “Feasibility Study of a Novel Asymmetric SGOI-TFET Using Non-Local BTBT Model,”Annual 11th IEEE
India International Conference (INDICON 2014), Pune, Maharastra, pp. 1-6, December 11-13, 2014.
5. Sweta Chander and S. Baishya, “A novel nanoscale FD SOI-TFET Architecture with Improved performanc,”3rd International Conference
nanotechnology- Innovative materials, Processes, Products and Applications (NANOCON 014), Bharti Vidyapeeth, Pune , Maharastra,
India, October 14-15 ,2014.

30 July 2022 78
5. Sweta Chander and S. Baishya, “Performance Analysis of Nanowire FET and tunnel FET with Different Channel Material in Nano
Regime,” 3rd International Conference nanotechnology- Innovative materials, Processes, Products and Applications (NANOCON 014),
Bharti Vidyapeeth, Pune , Maharastra, India, 14-15 October 2014.
6. Sweta Chander and S. Baishya,” A Comprehensive Analysis of SOI-TFET with Novel AlxGa1-xAs Channel Material,” IEEE 2nd
International Conference on Devices, Circuits and Systems, Karunya University, Tamilnadu, India, pp. 1-5, March 6-8, 2014.
7. Sweta Chander, Om Prakash Mahto, Vivek Chander and S. Baishya,” Analysis of Novel SGOI-TFET with Record Low Subthreshold
Swing (SS) and High Ion/Ioff Ratio,” 8th IEEE International Conference on Computing for Sustainable Global Development (INDIAcom
2014), Bharati Vidyapeeth, New Delhi, India, pp. 500-504, March 5-7, 2014.
8. Sweta Chander, Vivek Chander and S. Baishya,” Improved Miller Effect using Al0.2Ga0.8As as a novel channel material in SOI based
TFET,” IEEE International Conference on VLSI and Signal Processing, IIT Kharagpur, West Bengal, India, January 10-12, 2014.
9. Sweta Chander and S. Baishya, “Advantage of SOI-TFET with Channel Material of Al0.2Ga0.8As,” 10th National Conference on Solid
State Ionics (NCSSI 10), IIT Kharagpur, West Bengal, India, December 22-23, 2013.
10. Sweta Chander and S. Baishya, “Impact of Channel Length & Oxide Thickness Variation in an Asymmetric SGOI-TFET,” IEEE Asia-
Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia 2013), GITAM University, Visakhapatnam,
India, pp. 103-106, December 19-21, 2013.
11. Sweta Chander and S. Baishya, “SOI-TFET with Different Mole Fraction of Germanium,” International Conference on Advanced
Nanomaterials and Nanotechnology (ICANN 2013), IIT Guwahati, India, December 1-3, 2013.
Publications

7/30/2022 80
1. K. Moselund, H. Ghoneim, M. T. Björk, H. Schmid, S. Karg, E. Lörtscher, W. Riess, and H. Riel, “Comparison of VLS grown Si NW tunnel FETs with different gate stacks,” in Proc.
ESSDERC, pp. 448-451,2009
2. S. Mookerjea, R. Krishnan, S. Datta, and V. Narayanan, ”Effective Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation”, IEEE Trans. Electron Devices, vol. 56, no. 9,
pp. 2092-98, Sept. 2009.
3. K. Jeon, W.-Y. Loh, P. Patel, C. Y. Kang. J. Oh, A.Bowonder, C. Park, C. S. Park, C. Smith, P. Majhi, H.-H. Tseng, R. Jammy, T.-J. King Liu, and C. Hu, "Si tunnel transistors with a novel
silicided source and 46mV/dec swing," Symposium on VLSITechnology Digest, pp. 121-122, June 2010.
4. Dheeraj Mohata, Saurabh Mookerjea, Ashish Agrawal, Yuanyuan Li, Theresa Mayer, Vijaykrishnan Narayanan ,Amy Liu2, Dmitri Loubychev, Joel Fastenau, and Suman Datta,
“Experimental Staggered-Source and N+ Pocket-Doped Channel III–V Tunnel Field-Effect Transistors and Their Scalabilities” Applied Physics Express 4 ,024105, 2011.
5. Ram Asra, Mayank Shrivastava, Kota V. R. M. Murali, Rajan K. Pandey, Harald Gossner, and V. Ramgopal Rao, “A Tunnel FET for VDD Scaling Below 0.6 V With a CMOS-Comparable
Performance”, IEEE Transactions On Electron Devices, Vol. 58, No. 7, July 2011.
6. Kuo-Hsing Kao, Anne S. Verhulst, William G. Vandenberghe, Bart Sorée, Wim Magnus, Daniele Leonelli, Guido Groeseneken,, and Kristin De Meyer, “Optimization of Gate-on-
Source-Only Tunnel FETs With Counter-Doped Pockets” IEEE Transactions On Electron Devices, Vol. 59, No. 8, August 2012.
7. Min Hung Lee, Jhe-Cyun Lin, and Cheng-Ying Kao “Hetero-Tunnel Field-Effect-Transistors With Epitaxially Grown Germanium on Silicon” IEEE Transactions On Electron Devices, Vol.
60, No. 7, July 2013.
8. Anukool Rajoriya, Mayank Shrivastava, Harald Gossner, Thomas Schulz, and V. Ramgopal Rao, “Sub 0.5 V Operation of Performance Driven Mobile Systems Based on Area Scaled
Tunnel FET Devices” IEEE Transactions On Electron Devices, Vol. 60, No. 8, August 2013.
References

7/30/2022 81
ESSDERC, pp. 448-451,2009
pp. 2092-98, Sept. 2009.
60, No. 7, July 2013.
References

7/30/2022 82
ESSDERC, pp. 448-451,2009
pp. 2092-98, Sept. 2009.
60, No. 7, July 2013.
References

References
1.L. Y. Chen, Z. H. Ming, Z. Y. Ming, H. H. Yong, W. Bin, L. Y. Le, and Z. C. Yu, “Two-dimensional threshold voltage model
of a nanoscale silicon-on-insulator tunneling field-effect transistor,” Chin. Phys. B, vol. 22, no. 3, pp. 038501-6, 2013.
2.R. Vishnoi and M. J. Kumar, “2-D Analytical Model for the Threshold Voltage of a Tunneling FET with Localized Charges,”
IEEE Trans. Electron Devices, vol. 61, no. 9, pp. 3054-3059, Dec. 2014.
3.B. Bhowmick and S. Baishya, “A Physics–based Model for Electrical Parameters of Double gate Hetero-material Nano
Scale Tunnel FET,” IJAIS Journal, vol. 1, no. 3, pp. 25-32, Feb. 2012.
4.B. Bhushan, K. Nayak, and V. R. Rao, “DC Compact Model for SOI Tunnel Field-Effect Transistors,” IEEE Trans. Electron
Devices, vol. 59, no. 10, pp. 2635-2642, Oct. 2012.
5.N. Cui, L. Liu, Q. Xie, Z. Tan, R. Liang, J. Wang, and J. Xu, “A Two-Dimensional Analytical Model for Tunnel Field Effect
Transistor and Its Applications,” Jpn. J. Appl. Phys, vol. 52, pp. 044303-6, Apr. 2013.
6.T. N. Nguyen, “Small-geometry MOS transistors: Physics and modeling of surface- and buried-channel MOSFETs,”
Stanford ICL Tech. Rep., G545-2, 1984.
7.M. G. Bardon, H. P. Neves, R. Puers, and C. V. Hoof, “Pseudo-Two-Dimensional Model for Double-Gate Tunnel FETs
Considering the Junctions Depletion Regions,” IEEE Trans. Electron Devices, vol. 57, no. 4, pp. 827-834, Apr. 2010.
8.K. Boucart and A. M. Ionescu, "Threshold voltage in Tunnel FETs: physical definition, extraction, scaling and impact on IC
design," in Proc. ESSDERC, pp. 299-302, 2007.
9.W. M. Reddick and G. A. Amaratunga, "Silicon surface tunnel transistor,” Applied Physics Letters, vol. 67, no. 4, pp. 494-
496, May 1995.
10.Synopsys TCAD Sentaurus Device Manual, 2012.
11.R. Booth, M. White, H. Wong, and T. Krutsick, “The Effect of Channel Implants on MOS Transistor. Characterization,”
IEEE Trans. Electron Devices, vol. ED-34, no. 12, pp. 2501-2508, Dec. 1987.
83

References
12. Quinn, J., Kawamoto, G. &McCombe, B. Subband spectroscopy by surface channel tunneling.Surf.Sci. 73, 190–196
,1978.
13. Banerjee, S., Richardson W., Coleman J. &Chatterjee, A.A new three-terminal tunnel device.IEEE Electron Device
Lett.8, 347–349 ,1987.
14. Takeda, E., Matsuoka, H., Igura, Y. &Asai, S. A band to band tunneling MOS device B2T-MOSFET.Tech. Digest IEEE
Int. Electron Devices Meet. 402–405 ,1988.
15. Baba, T. Proposal for surface tunnel transistors.Jpn. J. Appl. Phys. 31, L455–L457,1992.
16. Reddick, W. &Amaratunga, G. Silicon surface tunnel transistor. Appl. Phys. Lett. 67, 494–496 ,1995.
17. Koga, J. &Toriumi, A. Negative differential conductance in three-terminal silicon tunneling device. Appl. Phys. Lett. 69,
1435–1437 ,1996.
18. Hansch, W., Fink, C., Schulze, J. &Eisele, I.A vertical MOS-gated Esaki tunneling transistor in silicon.Thin Solid Films
369, 387–389 ,2000.
19. Aydin, C. et al. Lateral interband tunneling transistor in silicon-on-insulator.Appl. Phys. Lett. 84, 1780–1782, 2004.
20. K. Bhuwalka, J. Schulze, I. Eisele, “Performance Enhancement of Vertical Tunnel Field-Effect Transistor with SiGe in
the dp+ Layer,” Jap. J. Appl. Phys., vol. 43, no. 7A, pp. 4073-4078, 2004.
21. Q. Zhang, W. Zhao, and A. Seabaugh, “Analytic Expression and Approach for Low Subthreshold-Swing Tunnel
Transistors,” Device Research Conference (DRC), June 20-22, Santa Barbara,CA, 2005.
22. K. Bhuwalka, M. Born, M. Schindler, M. Schmidt, T. Sulima, and I. Eisele, “P-Channel Tunnel Field-Effect
Transistors down to Sub-50 nm Channel Lengths,” Jap. J. Appl. Phys., vol. 45, no. 4B, pp. 3106-3109, 2006.
23. T. Nirschl, S. Henzler, J. Fischer, M. Fukle, A. Bargagli-Stoffi, M. Sterkel, J. Sedlmeir, C. Weber, R. Heinrich, U.
Schaper, J. Einfeld, R. Neubert, U. Feklmann, K. Stahrenberg, E. Ruderer, G. Georgakos, A. Huber, R. Kakoschke, W.
Hansch, D. Schmitt-Landsiedel, “Scaling properties of the tunneling field effect transistor (TFET): Device and circuit,”
Solid-State Elec., vol. 50, pp. 44-51, 2006.
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