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Spi in arm7(lpc2148)
The document discusses the Serial Peripheral Interface (SPI) protocol, describing its characteristics such as synchronous communication, master/slave configuration, and data transfer methods. It covers essential operations like read overrun, write collision, and mode faults that can occur during the SPI communication. Additionally, it provides initialization and data transfer functions for SPI in the LPC2148 microcontroller.
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The presentation introduces SPI in the ARM7 microcontroller LPC2148 by Aarav Soni.
SPI, a synchronous serial data protocol, is discussed. It features single master, multiple slaves, low power consumption, and a four-wire communication interface.
Details of the SPI controller include full duplex communication, support for data transfer rates of up to 1/8th input clock rate, and the roles of MISO, MOSI, SCK, and Slave Select.
The timing relationships between data, clocks, and phases in SPI are presented, summarizing the conditions for data transmission.
Explains conditions like read overrun and write collision in SPI communication, alongside their effects on data integrity.
Describes mode fault scenarios in SPI when the master’s SSEL is active and the implications of slave abort during data transfers.
Introduces the SPI Control Register (S0SPCR), detailing its configurations.
Introduces the SPI Status Register (S0SPSR) which provides status indicators for the SPI operations.
Covers the SPI Interrupt Register (S0SPINT) and its role in managing interrupts during SPI operations.
Provides a code example for SPI initialization, including pin selection and clock configuration for master mode.
Shows a function for receiving characters in SPI, illustrating data retrieval from the SPI data register.
The presentation concludes with thanks from Aarav Soni and contact information for further inquiries.
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Spi in arm7(lpc2148)
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- 2. What is SPI? • Serial Peripheral Interface (SPI) is a synchronous serial data protocol used by microcontrollers for communicating with one or more peripheral devices quickly over short distances. It can also be used for communication between two microcontrollers. • Low power than I2C (no need of Pull ups) • Supports Single master and multiple slaves • No hardware slave acknowledgement • Instrumentation & Communication Unit • designed by Motorola • four wire protocol
- 3. • Single completeand independent SPI controller. • Compliant with Serial Peripheral Interface (SPI) specification. • Synchronous, Serial, Full Duplex Communication. • Combined SPI master and slave. • Maximum data bit rate of one eighth of the input clock rate. • 8 to 16 bits per transfer • Master In Slave Out (MISO) - The Slave line for sending data to the master, • Master Out Slave In (MOSI) - The Master line for sending data to the peripherals, • Serial Clock (SCK) - The clock pulses which synchronize data transmission generated by the master, and • Slave Select pin - the pin on each device that the master can use to enable and disable specific devices. When a device's Slave Select pin is low, it communicates with the master. When it's high, it ignores the master .
- 8. • The dataand clock phase relationships are summarized in Table 197. This table • summarizes the following for each setting of CPOL and CPHA. • When the first data bit is driven • When all other data bits are driven • When data is sampled
- 9.
- 10. Read Overrun: A readoverrun occurs when the SPI block internal read buffer contains data that has not been read by the processor, and a new transfer has completed. The read buffer containing valid data is indicated by the SPIF bit in the status register being active. When a transfer completes, the SPI block needs to move the received data to the read buffer. If the SPIF bit is active (the read buffer is full), the new receive data will be lost, and the read overrun (ROVR) bit in the status register will be activated. Write Collision: As stated previously, there is no write buffer between the SPI block bus interface, and the internal shift register. As a result, data must not be written to the SPI data register when a SPI data transfer is currently in progress. The time frame where data cannot be written to the SPI data register is from when the transfer starts, until after the status register has been read when the SPIF status is active. If the SPI data register is written in this time frame, the write data will be lost, and the write collision (WCOL) bit in the status register will be activated.
- 11. Mode Fault: The SSELsignal must always be inactive when the SPI block is a master. If the SSEL signal goes active, when the SPI block is a master, this indicates another master ha selected the device to be a slave. This condition is known as a mode fault. When a mode fault is detected, the mode fault (MODF) bit in the status register will be activated, the SPI signal drivers will be de-activated, and the SPI mode will be changed to be a slave. Slave Abort A slave transfer is considered to be aborted, if the SSEL signal goes inactive before the transfer is complete. In the event of a slave abort, the transmit and receive data for the transfer that was in progress are lost, and the slave abort (ABRT) bit in the status register will be activated.
- 13. SPI Control Register(S0SPCR)
- 15. SPI Status Register(S0SPSR)
- 17. SPI Interrupt register(S0SPINT)
- 18. /********************************/ Function for initializingSPI /********************************/ void spi_init() { PINSEL0=0X00001505;// Select MOSI, MISO, SCK S0SPCCR=0X08; // clock is divided by 8 S0SPCR=0X0020; // select as master } /********************************/ Function for sending a char /********************************/ void spi_master(char a) { S0SPDR=a; while(!(S0SPSR & 0X80)); }
- 19. /********************************/ Function for receivinga char /********************************/ char spi_slave(void) { while(!(S0SPSR & 0X80)); return S0SPDR; }
- 20. Thanks For any suggestion, Pleasecontact me on- Mail id- [email protected] Facebook- https:www.facebook.com/arav.soni.98 Twitter- https://twitter.com/AaravSoni1