SPI introduction(Serial Peripheral Interface)
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The document provides a comprehensive overview of the Serial Peripheral Interface (SPI), a serial bus communication protocol developed by Motorola in the 1980s for short-distance communication. It describes the architecture, data transmission methods, signal descriptions, and configurations such as master-slave relationships and multi-slave setups, including daisy chain connections. Additionally, it details control and status registers, their functionalities, and options for low-power operation modes.
![SPI - Signal Descriptionsa
The SPI is four wire-based protocol,below are SPI pins used to interface to
external devices.
• MOSI (Master Out-Slave In)
• MISO (Master In-Slave Out)
• SCL (Serial clock which produces by the master)
• SS[n] (Slave select line which use to select specific slave
during the communication)](https://image.slidesharecdn.com/spiintroduction-200204061736/85/SPI-introduction-Serial-Peripheral-Interface-5-320.jpg)
SPI introduction(Serial Peripheral Interface)
- 1. SPI - Serial Peripheral Interface G.Sunodh Kumar Design Verification Enginner
- 2. SPI - Serial Peripheral Interface • SPI is Serial Bus Communication Protocol • It was first developed by Motorola in late 1980 and it is most popular serial synchronous bus protocol for short distance communication • Sometimes SPI called as four-wire serial bus and each bus has a specific role and importance. • The SPI can be multi-slave but it cannot be multi-master that means in SPI there must be only one master which control the all communication event and communication is always started by the master
- 3. SPI - Serial Peripheral Interface • In SPI master-slave both shared the same clock and clock is produced by the master. • SPI works in full-duplex mode, which means it can receive and send data at a time. • The serial peripheral interface, data is shifted out from the master and shifted into the master through the shift register. • SPI is synchronous data bus don't have start and stop bit, so there is no extra overhead on communication.
- 4. SPI - Serial Peripheral Interface • SPI is a primitive protocol without an acknowledgement mechanism for checking received or sent data. • Industry Standard(s) Compliance Statement The programmable configuration capability of the SPI allows it to gluelessly interface to a variety of SPI format devices. The SPI does not conform to a specific industry standard.
- 5. SPI - Signal Descriptionsa The SPI is four wire-based protocol,below are SPI pins used to interface to external devices. • MOSI (Master Out-Slave In) • MISO (Master In-Slave Out) • SCL (Serial clock which produces by the master) • SS[n] (Slave select line which use to select specific slave during the communication)
- 6. SPI - Data Transmission a a • To begin SPI communication, the master must send the clock signal and select the slave by enabling the SS signal. • Usually chip select is an active low signal; hence, the master must send a logic 0 on this signal to select the slave. • During SPI communication, the data is simultaneously transmitted (shifted out serially onto the MOSI/SDO bus) and received (the data on the bus (MISO/SDI) is sampled or read in). • The serial clock edge synchronizes the shifting and sampling of the data. • The SPI interface provides the user with flexibility to select the rising or falling edge of the clock to sample and/or shift the data.
- 7. SPI Data Transmission- Buffer & Shift Registera • Buffer act as interface between processor (or programmer) and SPI. • Buffer reg. will avoid all glitches that can happen if we try to read,write to shift register directly while trasmission taking place.
- 8. SPI - Shift Register a a • Usually shift register won't be directly accessible so,if we need to transmit data, we will write it to the buffer register.so,it is automatically written to shift register when it is free and transmission will start. • Similarly data is received in the shift register is automatically transferred to buffer register once the reception is complete. We can easily read from it.Thus we can avoid glitches in buffer registers.
- 9. SPI Transfer formats - Clock Polarity & Phasea • SPI communication data is driven in 4 modes decided by the combination of CPOL & CPHA. • Clock polarity(CPOL) - Designates the default value (high/low) of the SCK signal when the bus is idle. • Clock phase(CPHA) - Determines which edge of the clock data is sampled (rising/falling). • CPOL & CPHA has to match with SPI slaves for proper data transfer SPI Mode CPOL CPHA Clock Polarity in Idle State Clock Phase Used to Sample and/or Shift the Data 0 0 0 Logic Low Data sampled on rising edge and shifted out on the falling edge 1 0 1 Logic Low Data sampled on the falling edge and shifted out on the rising edge 2 1 0 Logic High Data sampled on the falling edge and shifted out on the rising edge 3 1 1 Logic High Data sampled on the rising edge and shifted out on the falling edge
- 10. SPI - Clock Polarity & Phase : Mode 0 Start & End of Transmission Sampling Edge Shifting Edge
- 11. SPI - Clock Polarity & Phase : Mode 1 Start & End of Transmission Sampling Edge Shifting Edge
- 12. SPI - Clock Polarity & Phase : Mode 2 Start & End of Transmission Sampling Edge Shifting Edge
- 13. SPI - Clock Polarity & Phase - Mode 3 Start & End of Transmission Sampling Edge Shifting Edge
- 14. SPI - Multi Slave Configurationsa Independent Slave Configuration • They is Independent slave line (CS1,CS2...) from master to each slave.SPI slave output MISO wil be tri-state pin,so it will be high impedance state when slave not selected. • Slave line CS will make low and keep rest of them high(you don't want two slaves activated at same time or they may both try to talk on same MISO line resulting in garbled data). • Lot of slaves required lot of SS(CS) lines.If you're running low on output,there are binary decoder or serial to parallel converters or demultiplexer that can multply your SS output or GPIOsa
- 15. SPI - Multi Slave Configurationsa Independent Slave Configurationa
- 16. SPI - Multi Slave Configurationsa Independent Slave Configuration - Decodera
- 17. SPI - Multi Slave Configurationsa Independent Slave Configuration - Demultiplexera
- 18. SPI - Multi Slave Configurationsa Independent Slave Configuration - Serial to Parallel Convertera
- 19. SPI - Multi Slave Configurationsa Daisy Chain Configuration • SPI can be connected one after another in serial form, In this configuration a single slave select line is used to select all daisy chain slaves. • Whole chain acts like communication through shift registers connected in series. • Each daisy chain slave is supposed to send out exact copy of data received in first group of clock cycles during second group of clock cycles.a
- 20. SPI - Multi Slave Configurationsa Daisy Chain Configurationa
- 21. Overview on SPI BLOCK NXP-Freescale Semiconductor, Inc.
- 23. SPI - Memory Map/Register Definitiona a • Register Address = base address + address offset. • The base address is defined at the SoC level and the address offset is defined at the module level.
- 24. SPI - Register Descriptions a a SPI Control Register 1 SPIE - SPI Interrupt Enable Bit A hardware interrupt is requested when either the receive buffer is full represented by Receive Buffer Full Flag (SPRF)=1 in the SPI Status register or when the slave select of the master MCU is pulled low causing a mode fault (MODF=1). 1 = SPI interrupts enabled 0 = SPI interrupts disabled.
- 25. SPI - Register Descriptions a a SPI Control Register 1 SPE - SPI System Enable Bit Turns the SPI on or off. Disable of SPI halts any transfer that is in progress, clears data buffers, and initializes internal state machines. The SPRF(SPI read buffer full flag in Status register) is cleared and the Transmit Data Buffer Empty Flag (SPTEF) in the SPIS is set to indicate that both buffers are empty. 1 = SPI enabled 0 = SPI disabled SPTIE - SPI Transmit Interrupt Enable A read/write bit that enables CPU interrupt requests to be generated when a byte transfers from the transmit data register to the shift register. 1 = SPTEF interrupt enabled (if SPTEF flag of status register is set). 0 = SPTEF interrupt disabled.
- 26. SPI - Register Descriptions a a SPI Control Register 1 MSTR - SPI Master/Slave Mode Select Bit Switching the SPI from master to slave or vice versa forces the SPI system into idle state. 1 = SPI is in Master mode 0 = SPI is in Slave mode LSBFE - SPI LSB-First Enable Reads and writes of the data register always have the msb in bit 7. 1 = Data is transferred least significant bit first. 0 = Data is transferred most significant bit first.
- 27. SPI - Register Descriptions a a SPI Control Register 1 SSOE - Slave Select Output Enable The SS output feature is enabled only in the master mode by asserting the SSOE.It is used in combination with the mode fault enable bit (MODFEN) in SPIC2 and the MSTR to determine the function of the SS_bar pin Note : In SPI control register_2 MODFEN is mode fault enable bit, MODFEN is set then MODF =1 & SPI is in master mode(MSTR=1) with SS line Low. MODFEN is cleared then in master mode SS is not used by SPI & don't mean MODF(mode fault in status registrer) clear. MODFEN SSOE Master Mode Slave Mode 0 0 SS not used by SPI SS input 0 1 SS not used by SPI SS input 1 0 SS input with MODF feature SS input 1 1 SS output SS input
- 28. SPI - Register Descriptions a a SPI Control Register 1a CPOL - SPI Clock Polarity Bit It is a read/write bit that determines the logic state of the SPSCK pin between transmissions. It effectively places or removes an inverter in series with the clock signal from a master SPI or to a slave SPI device. To transmit data between two SPI modules 1 = Active-low clocks selected. In idle state SCK is high. 0 = Active-high clocks selected. In idle state SCK is low. CPHA - SPI Clock Phase Bit It is a read/write bit that controls the timing relationship between the serial clock and SPI data. 1 = Sampling of data occurs at even edges (2,4,6,...,16) of the SCK clock 0 = Sampling of data occurs at odd edges (1,3,5,...,15) of the SCK clock NOTE: It is recommended that software writes to the SPI control register to change CPHA, CPOL or MSTR bits only in
- 29. SPI - Register Descriptions a a SPI Control Register 1 • In master mode, a change of CPOL,CPHA bit will abort a transmission in progress and force the SPI system into idle state. • In slave mode, the control bits CPHA and CPOL of the SPI should be configured only when SPI is disabled else it may lead to incorrect data transfer. Care must be taken to avoid driver collisions in SPI disabled state, because SPI port pins are then not under the control of the SPI. • When CPHA is set, the first edge is used to get the first data bit onto the MISO(serial data output pin). When CPHA is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data output pin. After the eighth shift, the transfer is considered complete and the received data is transferred into the SPI data register. To indicate transfer is complete, the SPIF flag in the SPI status register is set.
- 30. SPI - Register Descriptions a a SPI Control Register 2 The second SPI control register, SPIC2, is used to control optional features on the SPI system. Bits 7, 6, 5, and 2 are not implemented and always read 0.
- 31. MODFEN SSOE Master Mode Slave Mode 0 0 SS not used by SPI SS input 0 1 SS not used by SPI SS input 1 0 SS input with MODF feature SS input 1 1 SS output SS input SPI - Register Descriptions a a SPI Control Register 2 MODFEN - Mode Fault Enable Bit 1 = Enable setting the MODF error 0 = Disable the MODF error MODFEN together with the SSOE bit and the MSTR bit, determine how the SS_bar pin is used. Note that MODFEN is a read/write bit If SPI is enabled as master and the MODFEN bit is low, then the SS pin is not used by SPI If SPI is enabled as a slave,the SS is available only as an input regardless of the value of MODFEN.
- 32. SPI - Register Descriptions a a SPI Control Register 2 BIDIROE - Output enable in the Bidirectional mode of operation This bit along with the MSTR bit of SPCR1 is used to enable the output buffer when the SPI is configured in bidirectional mode. 1 = Output buffer enabled 0 = Output buffer disabled SPISWAI - SPI Stop in Wait Mode Bit It is a read/write bit that is used to either keep the SPI clocks running or stopped when the MCU enters WAIT mode. This reduces overall power consumption. 1 = Stop SPI clock generation when in wait mode 0 = SPI clock operates normally in wait mode
- 33. SPI - Register Descriptions a a SPI Control Register 2a SPC0 - Serial Pin Control Bit 0 SPC0 is a read/write bit that selects whether Single-wire Bidirectional mode or Full-duplex mode is enabled.With the MSTR control bit, this bit enables bidirectional pin configurations as shown in Table
- 34. SPI - Register Descriptions a a SPI Control Register 2a SPC0 - Serial Pin Control Bit 0 In bidirection mode, the SPI uses only one serial data pin for the interface with external device(s).
- 35. SPPR2 - SPPR0 are the three bits that select one of eight divisors for the SPI baud rate prescaler. The output of the prescaler drives the input of the SPI baud rate divider SPR2 - SPR0 are the three bits that select one of eight divisors for the SPI baud rate divider. The input to the divider comes from the SPI baud rate prescaler, and the output is the SPI bit rate clock (in Master mode). SPI - Register Descriptions a a SPI Baud Rate Register
- 36. SPI - Register Descriptions a a SPI Baud Rate Register
- 37. The baud rate generator is activated only when the SPI is in the master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease IDD current. SPPR2–SPPR0 - SPI Baud Rate Preselection Bits SPR2 – SPR0 - SPI Baud Rate Selection Bits The baud rate divisor equation is as follows Baud Rate Divisor = Baud Rate = Bus clock / BaudRateDivisor NOTE: Writing to this register during data transfers may cause spurious results SPI - Register Descriptions a a SPI Baud Rate Register
- 38. SPI - Register Descriptions a a SPI Status Register It is a read-only register that lets the processor know if either the read buffer or write buffer is full, or if a Master mode fault error has been detected. Writes to this register have no meaning or effect.
- 39. SPI - Register Descriptions a a SPI Status Register SPIF - SPIF Interrupt Flag This bit is set after the eighth SCK cycle in a data transfer and is cleared by reading the SPISR register (with SPIF set) followed by a read access to the SPI data register. 1 = New data Copied to SPIDR 0 = Transfer not yet complete SPTEF - SPI Transmit Empty Interrupt Flag The Transmit Buffer Empty Flag (SPTEF) is set when there is room in the transmit data buffer.If the SPTEF bit goes high, a CPU interrupt request is initiated as long as the SPTIE bit in the SPICR1 is also set high. 1 = SPI Data register empty 0 = SPI Data register not empty
- 40. SPI - Register Descriptions a a SPI Status Register a SPTEF - SPI Transmit Empty Interrupt Flag When a data byte transfers from the transmit buffer into the transmit shift register, the SPTEF bit is automatically set. For an idle SPI with no data in the transmit buffer or the shift register and no transfer in progress, data written to the data register is transferred to the shifter almost immediately. Therefore, SPTEF is set within two bus cycles allowing a new value to be queued into the buffer. After completion of the transfer of the value in the shift register, the queued value from the transmit buffer will automatically move to the shifter and the SPTEF will be set to indicate there is room for new data in the transmit buffer. If there is no data waiting in the buffer, the SPTEF bit simply remains high.
- 41. SPI - Register Descriptions a a SPI Status Register MODF - Mode Fault Flag If more than one master trying to drive the MOSI and SCK lines simultaneously. In this case, the SPI immediately clears the output buffer enables associated with the MISO, MOSI (or MOMI), and SCK pins so that these pins become inputs. The SS_bar pin will only act as a mode fault error input when the SPI is configured as a master, the MSTR bit = 0, the MODFEN bit = 0, and the SSOE bit = 0. Otherwise, MODF will never be set. Clearing the MODF bit is achieved by reading MODF when it is high and writing to the SPICR1. Mode fault doesn't occur in slave mode. 1 = Mode fault has occurred (If SS input becomes low while SPI is configured as a master) 0 = Mode fault has not occurred
- 42. SPI - Register Descriptions a a SPI Data Register Read: anytime; normally read only after SPIF is set Write: anytime; see SPTEF a The SPI Data register is both the input and output register for SPI data. A write to this register allows a data byte to be queued and transmitted. For a SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI Transmitter empty flag in SPISR indicates when the SPI data register is ready to accept new data.
- 43. SPI - Register Descriptions a a SPI Data Register Reading the data can occur anytime from after the SPIF is set to before the end of the next transfer. If the SPIF is not serviced by the end of the successive transfers, those data bytes are lost and the data within the SPIDR retains the first byte until SPIF is serviced. When a write to the SPI data register in the master occurs, there is a half SCK- cycle delay. After the delay, SCK is started within the master. The rest of the transfer operation differs slightly, depending on the clock format specified by the SPI clock phase bit, CPHA, in SPI control register 1
- 44. SPI - Low Power Mode Options a a The SPI functions in three modes, run, wait, and stop. Run Mode a This is the basic mode of operation.In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state. SPI registers can still be accessed, but clocks to the core of this module are disabled.
- 45. SPI - Low Power Mode Options a a Wait Mode a SPI operation in wait mode depends upon the state of the SPISWAI bit in SPICR2. • If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode • If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait mode. a. If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode entry. The transmission and reception resumes when the SPI exits wait mode. b. If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in progress continues if the SCK continues to be driven from the master. This keeps the slave synchronized to the master and the SCK.
- 46. SPI - Low Power Mode Options a a Wait Mode a If the master transmits several bytes while the slave is in wait mode, the slave will continue to send out bytes consistent with the its operation mode at the start of wait mode (i.e. If the slave is currently sending its SPIDR to the master, it will continue to send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte). NOTE: Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e. a SPIF interrupt will not be generated until exiting stop or wait mode). Also, the byte from the shift register will not be copied into the SPIDR register until after the slave SPI has exited wait or stop mode. A SPIF flag and SPIDR copy is only generated if wait mode is entered or exited during a transmission. If the slave enters wait mode in idle mode and exits wait mode in idle mode, neither a SPIF nor a SPIDR copy will occur.
- 47. SPI - Low Power Mode Options a a Stop Mode a • The SPI is inactive in stop mode for reduced power consumption. The STOP instruction does not affect or depend on SPI register states but dependent on the system. • The SPI enters stop mode when the module clock is disabled (held high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is exchanged correctly. In slave mode, the SPI will stay synchronized with the master. The stop mode is equivalent to the wait mode with the SPISWAI bit set except that the stop mode is dependent on the system and cannot be controlled with the SPISWAI bit.
- 48. SPI - Reseta a • The reset values of registers and signals are described in the Memory Map and Registers section • If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the byte last received from the master before the reset. • Reading from the SPIDR after reset will always read a byte of zeros. SPI - Frequencya a • The maximum Master mode frequency is half of the bus frequency. • In Slave mode, the maximum frequency is equal to the bus frequency divided by 4 to allow for oversampling and ensure accurate communication
- 49. SPI - Master Slave Initialization
- 50. SPI - Pros and cons: Advantages: • There is no start and stop bits, so the data can be streamed continuously without interruption. • It supports full-duplex. • No need for precision oscillators in slave devices as it uses a master’s clock. • No complicated slave addressing system like I2C. • Higher data transfer rate than I2C (almost twice as fast). • Separate MISO and MOSI lines, so data can be sent and received at the same time. • Simple software implementation Disadvantages: • If there is more than one slave in communication then the wiring will be complex. • Uses four wires (I2C and UARTs use two). • No acknowledgment that the data has been successfully received (I2C has this). • No form of error checking like the parity bit in UART. • It only allows for a single master.
- 51. Reference : • http://www2.eng.ox.ac.uk/~labejp/Robots/DataSheets/HCS12/S12SPIV2.pdf • https://electrosome.com/spi/ • https://www.analog.com/media/en/analog-dialogue/volume-52/number-3/introduction- to-spi-interface.pdf • http://dlnware.com/theory/SPI-Slave-Selection • http://dlnware.com/dll/Connecting-multiple-slave-devices • https://www.nxp.com/files-static/microcontrollers/doc/ref_manual/S12SPIV4.pdf
- 52. Thank You
Editor's Notes
- #4: Full Duplex(it will have two wire combining them have one tx,one rx ) is not same as bidirectional(have only one wire can tx,rx).
- #10: In SPI protocol one rule should be common for the slave and master. The data line should be sync to each other for example if MOSI line sample at the rising edge so MISO line should be a sample at the rising edge.
- #37: Note : -- The maximum Master mode frequency is half of the bus frequency. -- In Slave mode, the maximum frequency is equal to the bus frequency divided by 4 to allow for oversampling and ensure accurate communication.