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- 1. Unit 3, Module 3 Flip-Flops Conversion and Flip Flop ICs Instructor Dr. R. S. Khule, Department of Information Technology, Matoshri College of Engineering and Research Centre, Nashik.
- 2. Recap • We have seen the logic diagram, operation and truth table of JK, Master-Slave JK, D ,T Flip- flops. • We have also seen the procedure to derive excitation table for SR, D, JK and T Flip-Flop.
- 3. Contents • Conversion of one Flip Flop to another. • Flip- Flop ICs.
- 4. Module Objectives • Understand the procedure of conversion of one Flip-Flop to another. • Study the 7474 and 7476 Flip Flop ICs.
- 5. Module Outcomes • Convert the given Flip Flop to the specified Flip Flop • Know the 7474 and 7476 Flip Flop ICs
- 6. Flip Flop Conversion • The conversion from one type of flip flop to the other needs design of conversion logic which is done using the excitation tables and K map simplifications. Given flip- flop Flip-flop Conversion logic (Combinational circuit) General model used to convert one type of FF to the other { Flip-flop Data inputs } Outputs Required Flip- Flop Q Q _
- 7. Truth Table of Conversion Logic • The truth table of the conversion logic has data inputs and Q and Q outputs of the given FF as inputs whereas the inputs of the given FF are the outputs of the truth table. • Then we draw the K map for each output and obtain the simplified expressions. • The conversion logic is then implemented using gates.
- 8. SR to D Flip flop Conversion
- 9. SR to D Flip flop Conversion 0 0 1 X Qn D 0 1 D D Qn 0 S D Qn 1 K-map for S X 1 0 0 Qn D 0 1 D D Qn 0 Qn 1 K-map for R R D Excitation Table for SR Flip Flop Input Present state Next state Flip flop Inputs D Q n Qn+1 S R 0 0 0 0 X 0 1 0 0 1 1 0 1 1 0 1 1 1 X 0 Truth Table of conversion Logic
- 10. D Q Q PR CR CLK S R D Flip-Flop Using SR Flip Flop Q Q
- 11. SR Flip flop to T Flip flop
- 12. Conversion of SR Flip flop to T Flip flop 0 x 1 0 Qn T 0 1 T T Qn 0 S TQn Qn 1 K-map for S X 0 0 1 Qn T 0 1 T T Qn 0 Qn 1 K-map for R R TQn Excitation Table for SR Flip Flop Input Present state Next state Flip flop Inputs T Q n Qn+1 S R 0 0 0 0 X 0 1 1 X 0 1 0 1 1 0 1 1 0 0 1
- 13. T Q Q PR CR CLK S R T Flip-Flop Using SR Flip Flop Q Q
- 14. SR Flip Flop to JK Flip Flop
- 15. SR Flip Flop to JK Flip Flop Excitation Table for SR Flip Flop Inputs Outputs J K Present state Qn Next state Qn+1 S R 0 0 0 0 0 × 0 0 1 1 × 0 0 1 0 0 0 × 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 1 × 0 1 1 0 1 1 0 1 1 1 0 0 1
- 16. 0 0 1 1 X 0 0 X JK Qn 0 1 00 01 11 10 S=J Qn X X 0 0 0 1 1 0 JK Qn 0 1 00 01 11 10 K-map for S K-map for R R=K Qn
- 17. SR Flip Flop to JK Flip Flop SR-FF S R Q Q CLK J K Q Q
- 18. JK to T Flip flop Conversion
- 19. JK to T Flip flop Conversion 0 x 1 X Qn T 0 1 T T Qn 0 J T Qn 1 K-map for J X 0 X 1 Qn T 0 1 T T Qn 0 Qn 1 K-map for K K=T Excitation Table for JK Flip Flop Input Present state Next state Flip flop Inputs T Q n Qn+1 J K 0 0 0 0 X 0 1 1 X 0 1 0 1 1 X 1 1 0 X 1
- 20. T Q Q PR CR CLK Q JK-FF Q J K T Flip-Flop Using JK Flip Flop
- 21. D Flip Flop to JK Flip Flop
- 22. D Flip Flop to JK Flip Flop Inputs Outputs J K Present state Qn Next state Qn+1 D 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 1 1 0 0 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 0
- 23. 0 0 1 1 1 0 0 1 JK Qn 0 1 00 01 11 10 D= K Qn + JQn K-map for D
- 24. D Flip Flop to JK Flip Flop D-FF D Q Q CLK J K Q Q
- 25. IC 7474 – Dual D Type Positive Edge triggered FF • IC 7474 – Dual Positive Edge triggered D Flip Flop with PRESET and CLEAR. • These IC contain two independent D-type positive edge triggered flip flops. 25
- 26. IC 7474 – Dual D Type Positive Edge triggered FF D-FF CLK D Q Q C R P R 2 3 4 1 5 6 D-FF CLK D Q Q C R P R 12 11 10 13 9 8 +Vcc = Pin 14 GND = Pin 7 Connection Diagram
- 27. IC 7474 –Function Table Operating Mode Inputs Outputs P R C R D Q Q Preset L H X H L Clear H L X L H Undetermined L L X H H Set H H H H L Reset H H L L H
- 28. • This device contains two independent positive pulse triggered J- K flip-flops with complementaryoutputs. • On the positive transition of the clock, the data from the J and K inputs is transferred to the master. • On the negative transition of the clock, the data from the master is transferred to the slave. • A LOW logic level on the preset or clear inputs will set or reset the outputs regardless of logic levels of other inputs IC 7476-DualMaster-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs
- 29. IC 7476 – Dual JK Flip Flop with Set and Clear Connection Diagram:
- 30. CLK C R K Q D-FF J Q 1 4 P R 16 2 3 15 14 +Vcc = Pin 5 GND = Pin 13 IC 7476 – Dual JK Flip Flop with Set and Clear CLK C R K Q D-FF J Q 6 9 P R 12 7 8 11 10
- 31. IC 7476 – Dual JK Flip Flop with Set and Clear Operating Mode Inputs Outputs P R C R J K Q Q Preset L H X X H L Clear H L X X L H Undetermined L L X X H H Toggle H H H H Q Q Reset H H L H L H Set H H H L H L Hold H H L L Q Q
- 34. Assignment Q.1 Convert T Flip Flop to D Flip Flop Q.2 Convert JK to SR Flip Flop Q.3 Convert D Flip Flop to SR Flip Flop Q.4 Design and implement T flip-flop using SR flip-flop.
- 35. • In next session i.e. Module 4 of Unit 3, we will discussed about synchronous and asynchronous counter.
- 36. Thank You