Stick Diagrams design and lamda dia.pptx
- 1. STICK DIAGRAM AND LAYOUT DESIGN RULES Presented By Prof. R. K. Chauhan Department of Electronics and Communication Engineering Subject- VLSI Design Subject code-BEC-401 Session-2024-25
- 3. Stick Diagrams VLSI design aims to translate circuit concepts onto silicon. stick diagrams are a means of capturing topography and layer information using simple diagrams. Stick diagrams convey layer information through colour codes (or monochrome encoding). Acts as an interface between symbolic circuit and the actual layout. Does show all components/vias. It shows relative placement of components. Goes one step closer to the layout Helps plan the layout and routing A stick diagram is a cartoon of a layout. Prof. R K. Chauhan Deptt of ECE, MMMUT Gorakhpur
- 4. Contd….. Does not show • Exact placement of components • Transistor sizes • Wire lengths, wire widths, tub boundaries. • Any other low level details such as parasitics.. Prof. R K. Chauhan Deptt of ECE, MMMUT Gorakhpur
- 5. 5 Stick Diagrams – Notations Metal 1 poly ndiff pdiff Metal 2 Contact Prof. R K. Chauhan Deptt of ECE, MMMUT Gorakhpur
- 6. 6 Stick Diagrams – Some rules Rule 1. When two or more ‘sticks’ of the same type cross or touch each other that represents electrical contact. Prof. R K. Chauhan Deptt of ECE, MMMUT Gorakhpur
- 7. 7 Contd… Rule 2. When two or more ‘sticks’ of different type cross or touch each other there is no electrical contact. (If electrical contact is needed we have to show the connection explicitly). Prof. R K. Chauhan Deptt of ECE, MMMUT Gorakhpur
- 8. 8 Contd….. Rule 3. When a poly crosses diffusion it represents a transistor. Note: If a contact is shown then it is not a transistor. Prof. R K. Chauhan Deptt of ECE, MMMUT Gorakhpur
- 9. 9 Y A VDD Y GND S D S D A HOW TO DRAW STICK DIAGRAM CMOS Inverter Stick diagram Prof. R K. Chauhan Deptt of ECE, MMMUT Gorakhpur
- 10. 10 CONTD….. CMOS two input NOR gate S D S D D S S D VDD GND OUT A B Prof. R K. Chauhan Deptt of ECE, MMMUT Gorakhpur
- 12. INTRODUCTION Layout-design describes how small feature device can be integrated and how closely they can be packed in a particular manufacturing process. Popularly there are two methods to describe any layout design (a) Micron (b) λ-Based design rule In λ-based design rule λ is actually the resolution of process. It is generally half of the minimum drawn transistor channel length. This is also the minimum width of a polysilicon wire. Designers often describe a process by its feature size. Feature size refers to minimum channel length, so λ is half the feature size. Prof. R K. Chauhan Deptt of ECE, MMMUT Gorakhpur
- 13. LAYOUT RULES Metal and diffusion have minimum width and spacing of 4λ as shown in Fig.1 Contacts are 2λ by 2λ and must be surrounded by 1λ on the layers above and below (Fig.1) Polysilicon uses a width of 2λ (Fig.1) Polysilicon overlaps diffusion by 2λ where a transistor is desired and has a spacing of 1λ away where no transistor is desired (Fig.1). Polysilicon and contacts have spacing of 3λ from other polysilicon or contacts. n-well surrounds pOS transistor by 6λ and avoid nMOS transistor by 6λ. Prof. R K. Chauhan Deptt of ECE, MMMUT Gorakhpur
- 14. Contd…. Transistors dimensions are usually defined in terms of Width to length (W/L) ratio. In Fig. 2a the transistor W/L ratios is defined as 4:2. For 0.18 micron technology the dimension of λ = 0.18 μm and therefore the channel length is 0.36 μm and width is 0.72 μm. It can be seen that the spacing between two transistor i.e. nMOS and pMOS is 12λ. Fig.2b shows pMOS transistor of W/L ratio as 8:2, where as the W/L ratio of nMOS transistor is 4:2. Prof. R K. Chauhan Deptt of ECE, MMMUT Gorakhpur
- 15. AREA ESTIMATION Stick diagrams can easily be drawn compared to complete layout of any circuits because they do not need to be drawn to scale. But, with the practice it is easy to estimate the area of a layout from the corresponding stick diagram. Layout area is usually determined by the metal wires. Transistors are small widths that fit under the wires. Wires having a width of 4λ and spacing of 4λ to the next wire, the track pitch are in all 8λ. This pitch also leaves room for a transistor to be placed between the wires. Therefore, as a thumb rule, it is reasonable to estimate the height and width of a cell by counting the number of metal tracks and multiply by 8λ. The spacing required between two transistors(nMOS and pMOS) is 12λ i.e. because of the well used. This spacing could be utilized for additional track whether wire is needed or not. Prof. R K. Chauhan Deptt of ECE, MMMUT Gorakhpur
- 16. Contd….. Fig.2b shows layout of a three input CMOS NAND gate. The area required for a cell of three input NAND gate is 40λ by 32λ. Prof. R K. Chauhan Deptt of ECE, MMMUT Gorakhpur
- 17. PRACTICE QUESTIONS Q1. Draw the layout of CMOS inverter in which the W/L ratio of pMOS is 8/2 and nMOS is 4/2. Prof. R K. Chauhan Deptt of ECE, MMMUT Gorakhpur
- 18. PRACTICE QUESTIONS Q2. Implement the function F, by CMOS gates and estimate the area required from its layout. Prof. R K. Chauhan Deptt of ECE, MMMUT Gorakhpur
- 19. PRACTICE QUESTIONS Q3. Sketch stick diagram of a 4-input CMOS NOR gate and draw its layout. Calculate the gate area.
- 20. PRACTICE QUESTIONS Q4. Consider the design of a CMOS compound OR-AND-INVERT gate computing Prof. R K. Chauhan Deptt of ECE, MMMUT Gorakhpur