Successive approximation adc
- 2. A successive-approximation ADC is a type of analog-to-digital converter that converts a continuous analog waveform into a discrete digital representation using a binary search through all possible quantization levels before finally converging upon a digital output for each conversion.
- 4. One of the most common analog-to-digital converters used in applications requiring a sampling rate under 10 MSPS is the Successive Approximation Register ADC. This ADC is ideal for applications requiring a resolution between 8-16 bits.
- 5. The SAR ADC does the following things for each sample: The analog signal is sampled and held. For each bit, the SAR logic outputs a binary code to the DAC that is dependent on the current bit under scrutiny and the previous bits already approximated. The comparator is used to determine the state of the current bit. Once all bits have been approximated, the digital approximation is output at the end of the conversion (EOC). The SAR operation is best explained as a binary search algorithm. Consider the code shown below. In this code, the current bit under scrutiny is set to 1. The resultant binary code from this is output to the DAC. This is compared to the analog input. If the result of the DAC output subtracted from the analog input is less than 0 the bit under scrutiny is set to 0.
- 6. if we consider the example of an analog input value of 0.425 V and a voltage reference of 1 V, we can approximate the output of an 8 bit ADC as follows: Set first bit of 8 bit output to 1 so output to DAC is 0.5 0.5 subtracted from 0.425 is less than 0, so set the first bit of output to 0 Set second bit of 8 bit output to 1, so output to DAC is 0.25 0.25 subtracted from 0.425 is greater than 0, so second bit of output is 1 Set third bit of 8 bit output to 1, so output to DAC is 0.375 0.375 subtracted from 0.425 is greater than 0, so third bit of output is 1 This process is repeated for all 8 bits until the output is determined to be: 01101100
- 7. It becomes apparent from this process that an N-bit SAR ADC must require N clock periods to successfully approximate the output. As a result of this, although these ADCs are low power and require very little space, they are not suitable for high speed, high resolution applications. Because these ADCs require very little space, they are often found as a peripheral inside microcontrollers or in an extremely small package. Perhaps slightly less intuitive is the fact that power dissipation scales with sampling rate. As a result of this, these ADCs are ideal for use in low power applications where the ADC is required to take samples infrequently. One thing to note in this architecture is the lack of a pipeline and the latency associated with this. As a result, the SAR ADC is suited to multiplexed applications. The two features of the ADC that define the overall characteristics of the ADC are not surprisingly, the DAC and the Comparator.
- 8. Strengths of the SAR ADC Low power consumption Physically Small Weaknesses of the SAR ADC Low sampling rates for high resolutions Limited resolution due to limits of DAC and Comparator Size increases with number of bits Applications of the SAR ADC Ideal for multichannel data acquisition systems with sampling frequencies under 10 MHz and resolutions between 8-16 bits.