System verilog control flow

INTRODUCTION:
System Verilog has the following types of control flow within a
process:
• Selection, loops and jumps : Sv adds c-Like do...while,
break, continue
• Task and function calls : Sv adds return
• Sequential and parallel blocks
• Timing control

SELECTION STATEMENTS:
• In Verilog, an if (expression) is evaluated as a boolean, so that
if the result of the expression is 0 or X, the test is considered
false.
• Sv adds the keywords unique and priority, which can be used
before an if.
• If either keyword is used, it shall be a run-time error for no
condition to match unless there is an explicit else.

UNIQUE IF:
• Unique if evaluates all the conditions parallel.
• In the following conditions simulator issue a run time
error/warning,
• More than one condition is true
• No condition is true or final if doesn’t have corresponding
else

PRIORITY IF:
• Priority if evaluates all the conditions in sequential order.
• In the following conditions simulator issue a run time
error/warning
• No condition is true or final if doesn’t have corresponding
else.

WHILE LOOP:
• Execution of statements within the loop happens only if the
condition is true.

DO WHILE LOOP:
• The condition will be checked after the execution of statements
inside the loop.

FOREACH LOOP:
• System Verilog foreach specifies iteration over the elements of
an array.
• The loop variable is considered based on elements of an array
and the number of loop variables must match the dimensions
of an array.
• Foreach loop iterates through each index starting from index 0.
Syntax: foreach(<variable>[<iterator>]]) begin
statement - 1
...
statement - n
end

FOR LOOP:
• System Verilog for loop is enhanced for loop of Verilog.
In Verilog,
• the control variable of the loop must be declared before the loop
• allows only a single initial declaration and single step assignment
within the for a loop
System Verilog for loop allows,
• declaration of a loop variable within the for loop
• one or more initial declaration or assignment within the for loop
• one or more step assignment or modifier within the for loop

FOR LOOP:
Syntax: for(initialization; condition; modifier) begin
statement - 1
...
statement - n
end
• Initialization: executed first, and only once. This allows the user
to declare and initialize loop control variables.
• Condition: the condition is evaluated. If it is true, the body of
the loop is executed, else the flow jumps to the statement after
the ‘for’ loop.
• Modifier: at the end of each iteration it will be executed, and
execution moves to Condition.

REPEAT LOOP:
• Repeat will execute the statements within the loop for a loop
variable number of times.
• If the loop variable is N, then the statements within the repeat
block will be executed N number of times.
Syntax: repeat(<variable>) begin
statement - 1
...
statement - n
end

FOREVER LOOP:
• As the name says forever loop will execute the statements
inside the loop forever.
• It can be said as indefinite iteration.
Syntax: forever begin
statement - 1
...
statement - n
end

BREAK AND CONTINUE STATEMENTS:
Break:
• The execution of a break statement leads to the end of the
loop.
• break shall be used in all the loop constructs (while, do-while,
foreach, for, repeat and forever).
Continue:
• Execution of continue statement leads to skip the execution of
statements followed by continue and jump to next loop or
iteration value.

BREAK AND CONTINUE STATEMENTS:

TASKS:
• Tasks and Functions provide a means of splitting code into
small parts.
• A Task can contain a declaration of parameters, input
arguments, output arguments, in-out arguments, registers,
events, and zero or more behavioral statements.
System Verilog task can be:
• static
• automatic

TASKS:
Static tasks:
• Static tasks share the same storage space for all task calls.
Automatic tasks:
• Automatic tasks allocate unique, stacked storage for each task
call.
System Verilog allows,
• to declare an automatic variable in a static task
• to declare a static variable in an automatic task
• more capabilities for declaring task ports
• multiple statements within task without requiring a begin…end or
fork…join block
• passing values by reference, value, names, and position
• the default direction of argument is input if no direction has been specified

FUNCTIONS:
• A Function can contain declarations of range, returned type,
parameters, input arguments, registers, and events.
• A function without a range or return type declaration returns a
one-bit value.
• Functions cannot contain any time-controlled statements, and
they cannot enable tasks.
• Functions can return only one value.
System Verilog function can be:
• Static
• automatic

FUNCTIONS:
Static Function:
• Static functions share the same storage space for all function
calls.
Automatic Function
• Automatic functions allocate unique, stacked storage for each
function call.
• System Verilog allows,
• to declare an automatic variable in static functions
• to declare the static variable in automatic functions

FUNCTIONS:
• more capabilities for declaring function ports.
• multiple statements within a function without requiring a
begin…end or fork…join block.
• returning from the function before reaching the end of the
function.
• Passing values by reference, value, names, and position.
• default argument values, function output and inout ports.
• the default direction of argument is input if no direction has
been specified.
• default arguments type is logic if no type has been specified.

TASKS AND FUNCTIONS:
System Verilog provides passing arguments to functions and
tasks:
• Argument pass by value
• Argument pass by reference
• Argument pass by name
• Argument default values:

Argument pass by value:
• The argument passing mechanism works by copying each
argument into the subroutine area.
• if any changes to arguments within the subroutine, those
changes will not be visible outside the subroutine.
Argument pass by Reference:
• As the argument within a subroutine is pointing to an original
argument, any changes to the argument within subroutine will
be visible outside.
• To indicate argument pass by reference, the argument
declaration is preceded by keyword ref.

Argument pass by name:
• In argument pass by name, arguments can be passed in any
order by specifying the name of the subroutine argument.
Argument default values:
• The default value can be specified to the arguments of the
subroutine.
• In the subroutine call, arguments with a default value can be
omitted from the call.
• if any value is passed to an argument with a default value, then
the new value will be considered.

MAIN DIFFERENCE B/W FUNCTIONS AND
TASK:

SEQUENTIAL AND PARALLEL BLOCKS

SEQUENTIAL BLOCK:
The System Verilog contains two types of blocks:
Sequential (begin-end blocks):
• All statements within sequential blocks are executed in the order in which they
are given. If a timing control statement appears within a block, then the next
statement will be executed after that delay.
Example: begin
a = 1;
#10 a = 0;
#5 a = 4;
end
• During the simulation, this block will be executed in 15 time units. At time 0,
the 'a' variable will be 1, at time 10 the 'a' variable will be 0, and at time 15
(#10 + #5) the 'a' variable will be 4.

PARALLEL BLOCK:
Parallel (fork-join blocks):
• All statements within parallel blocks are executed at the same time. This
means that the execution of the next statement will not be delayed even if
the previous statement contains a timing control statement.
Example: fork
a = 1;
#10 a = 0;
#5 a = 4;
join
• During the simulation this block will be executed in 10 time units. At time 0
the 'a' variable will be 1, at time 5 the 'a' variable will be 4, and at time 10
the 'a' variable will be 0.

PARALLEL BLOCKS:
Fork_join:
• Fork-Join will start all the processes inside it parallel and wait
for the completion of all the processes.
Fork join_any:
• Fork-Join_any will be unblocked after the completion of any of
the Processes.
Fork join_none:
• As in the case of Fork-Join and Fork-Join_any fork block is
blocking, but in case of Fork-Join_none fork block will be non-
blocking.

PARALLEL BLOCKS:
Wait fork:
• Causes the process to block until the completion of all
processes started from fork blocks.
Disable fork:
• Causes the process to kill/terminate all the active processes
started from fork blocks.

TIMING CONTROL:
Delay controls:
• Delays the execution of a procedural statements by specific
simulation time.
Syntax: #<time><statement>;
Edge sensitive event control:
• Delays execution of the next statement until the specified
transaction on a signal.
Syntax: @(<posedge>|<negedge>)<statement>;

TIMING CONTROL:
Level sensitive event controls: (wait statements):
• Delays execution of the next statement until expression
evaluates to true.
Syntax: wait(<expression>)<statement>;
Events:
• Events are useful for synchronization between the process.
Events operations are of two staged processes in which one
process will trigger the event, and the other processes will wait
for an event to be triggered.
• Events are triggered using -> operator or ->> operator

NAMED BLOCKS:
• Named blocks in Verilog are allowed for begin and fork. They
can be added only after the reserve word begin and fork.
Example:
 begin : "MY_NAMED_BLOCK1"
 fork : "MY_NAMED_BLOCK2"

NAMED BLOCKS:
• System Verilog allows to add the LABLE or NAMED BLOCK
before begin, fork.
Example:
• "MY_NAMED_BLOCK" : begin
• "MY_NAMED_BLOCK" : end
• "MY_NAMED_BLOCK" : fork
• "MY_NAMED_BLOCK" : join

DISABLE BLOCK:
• Sv has break and continue to break out of or continue the
execution of loops. The Verilog-2001 disable can also be used
to break out of or continue a loop,.
• The disable is also allowed to disable a named block, which
does not contain the disable statement.
• If the block is currently executing, this causes control to jump
to the statement immediately after the block.
• If the block is a loop body, it acts like a continue. If the block is
not currently executing, the disable has no effect.

NON BLOCKING & BLOCKING:
Nonblocking assignment:
• non-blocking assignment statements execute in parallel.
• In the non-blocking assignment, all the assignments will occur
at the same time.
Blocking Assignment:
• Blocking assignment statements execute in series order.
Blocking assignment blocks the execution of the next
statement until the completion of the current assignment
execution.

System verilog control flow

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