Making of an Application Specific Integrated Circuit

THE MAKING OF AN ASIC
The process of designing and productionising a mixed signal
application specific integrated circuit with SWINDON Silicon Systems
www.swindonsilicon.co.uk

Contents
An informative guide to
the process of designing
and productionising a
mixed signal
application specific
integrated circuit
with
SWINDON Silicon Systems
Production
Qualification
Test Development
Evaluation
Processing
Design and Layout
Specification
The Design Process

The Design Process - Part 1
The ASIC Development Process provides a proven
roadmap for complete Product Development
1. Application Review
 Review of your system requirements
 Establish ASIC requirements
2. ASIC Quotation
 Non-Recurring Engineering (NRE)
 Estimated Unit Price (in Production)
 Development Schedule
3. Preliminary Design Review
 Review Block Diagram
 Establish Specification
 Establish Packaging Requirements
 Establish Test Requirements
 Review Schedule
 Establish Target Die Size
 Establish Fabrication Process
4. Initial Design & Layout
 Complete Critical Circuits design
 Complete preliminary ASIC Floor Plan
 Complete Built-In Test features
5. Critical Design Review
 Review Critical Circuit performance
 Report physical layout status
6. Final Design & Layout
 Complete Cell Level designs
 Complete Top Level design
 Simulate over temperature | voltage
 Complete Design Rule Checks (DRC's)
 Complete Layout vs. Schematic (LVS)
 Prepare Test Plans

The Design Process – Part 2
The ASIC Development Process provides a proven
roadmap for complete Product Development
7. Final Design Review
 Review Simulations
 Review Test Plans
 Review Physical Layout
 Proceed to Fabrication
8. Prototype Fabrication
 Mask Fabrication
 Silicon Fabrication
9. Test Program Development
 Prototype Test Program
 Preliminary Production Test Program
10. Prototype Evaluation
 SWINDON tests Prototype at wafer
probe
 SWINDON tests Prototype in
package
 Customer evaluates Prototype
11. Prototype Acceptance Review
 ASIC performance versus
Specification
 Reliability Testing Review
 Yield Analysis Review
 Proceed to Production

The Importance of Specification
The specification phase is an extremely
important part of the design process as any
errors that occur here will be magnified
further down the process.
That is why SWINDON assists its customers in
developing the systems specification and
advises as to what can be achieved on chip.
The full ASIC specification is then produced
by the relevant SWINDON technical lead
engineer and this will be signed off by all
parties concerned.
This extensive process usually takes
between 4 and 12 weeks depending upon
the complexity of the device that is being
designed.

The Specification Process
1. Review of the system schematics, block
diagrams and specifications.
2. Develop an understanding of the design
challenges, operating environment and
regulatory requirements
3. Understand the final product (not just the
ASIC) including any certification
requirements such as IEC, TS compliance.
4. Produce an ASIC block diagram and full
specification that states full operational
parameters and pin out and any required
external components.
5. Identify board level architectural trade-
offs that lead to most cost effective silicon
integration.

Design
A simplistic example
1 • Assign Technical Lead, Project Manager and Design Team
2 • Determine process
3 • System level design, block specification and Floor plan
4 • Block level design/simulation and IP block insertion
5 • Design for Test (DFT)
6 • Synthesis and verification
7 • Layout
8 • DRC and LVS
9 • Tapeout

1. Design and Layout
System level
design block
specification
• A top down design approach is adopted for the Project
• Partitioning the chip into functional blocks
• Defining their functionality and writing a specification for
each block
• Writing a behavioural model (analogue or digital), which is
used to verify that the design meets its requirements.
• Writing a simulation plan which describes the method of
proving the design correctness
Floor plan
• A top level chip floor plan is produced that defines the area
and shape of each functional block. Along with its
interconnection to other blocks. The block areas are design
goals for each block. These terms will be assessed and the
floor plan updated as the project progresses.

For mixed signal designs there are
2 procedures run in parallel: Analogue | Digital
Block level design /
simulation
• Analogue Design
• Circuit blocks are designed at the transistor
level and simulated using a HSPICE
compatible simulator.
• Simulation results are verified against the
block specification and the VerilogA
behavioural model.
• Digital Design
• Writing a synthesizable RTL (register
transfer level) description (either on
Verilog or VHDL) of the device.
• Writing a behavioural model, which is used
to verify that the design meets its
requirements.
• Writing a verification plan and a
corresponding verification environment
which describes and implements the
method of proving the design correctness

Verification
• The RTL description is verified
against the behavioural model.
• This approach reduces the
probability of the design error
since no RTL designer tests his
own code.

Design for Test
(DFT)
•Most mixed signal ASIC designs are complex require built
in assistance in order to be able to production test
effectively. These preparations are called DFT (design for
test).
•For the analogue sections it is important that key signals
can be observed in the analogue blocks. This may require
the routing of internal test points to device pads.
•For the Digital section of the design DFT techniques
include:
•Scan path insertion - a methodology of linking all
registers into one long shift register (scan path). This can
be used to check small parts of design instead of the
whole design (the latter being almost always
impossible).
•BIST (built-in self test) - a device used to check RAMs.
After being triggered it feeds specific test patterns to the
RAM module, reads back and compares results.
•ATPG (automatic test pattern generation) - a method of
creating test vectors for scan paths and BIST
automatically. Most modern EDA tool chains
incorporate such a feature.

Synthesis
• The synthesizable and verified RTL undergo logic synthesis. The
synthesized reads RTL input, user-specified constraints and a
cell library from the foundry. The output of the synthesis
process is a gate-level netlist.
Netlist
• The netlist must undergo formal verification to prove that RTL
and netlist are equivalent.
Checks
• Preliminary timing results after synthesis are analysed, critical
paths are checked against the project performance
requirements. If needed, the RTL description, constraints or
synthesis options are modified, and the synthesis is repeated.

Layout
• Analogue
•This often requires hand crafting of the layout at
a transistor level to construct customised
analogue functions .
•The size and shape being dictated by the floor
plan. These blocks can subsequently be
interconnected at the top level.
•On completion of the blocks the circuits will be
back-extracted and re-simulated in order to
account for layout parasitics.
• Digital
•When timing constraints are finally met, the
design proceeds to the layout, which consists of
floor planning, placement and routing.
• Some other important tasks are performed at
this step, including clock tree insertion.

DRC
and LVS
• The last stage before tape out includes the
following checks:
• DRC (design rule check) is a check that the layout
conforms to the foundry-specific rules.
• LVS (layout versus schematic) is a formal equivalence
check between the post-synthesis netlist and the final
layout.
Tapeout
• At last the resulting layout in GDSII format is
handed to the semiconductor fabrication plant
(foundry).
• This process is called tape out.

1. Wafer Processing
The Czochralski Process
 A typical wafer is made out of extremely
pure silicon that is grown into mono-
crystalline cylindrical ingots (boules) up to
300 mm (slightly less than 12 inches) in
diameter using the Czochralski process.
 These ingots are then sliced into wafers
about 0.75 mm thick and polished to
obtain a very regular and flat surface.
 Once the wafers are prepared, many
process steps are necessary to produce
the desired semiconductor integrated
circuit. In general, the steps can be
grouped into two major parts:
Front-end-of-line (FEOL) processing
Back-end-of-line (BEOL) processing

2. Wafer Processing
Deposition
 Any process that grows, coats, or
otherwise transfers a material onto
the wafer.
 Available technologies consist of
 Physical vapour deposition (PVD)
 Chemical vapour deposition (CVD)
 Electrochemical deposition (ECD)
 Molecular beam epitaxy (MBE)
 More recently, atomic layer
deposition (ALD) …among others.
Removal processes
 Any that remove material from the
wafer either in bulk or selectively and
consist primarily of etch processes,
either wet etching or dry etching.
 Chemical-mechanical planarisation
(CMP) is also a removal process used
between levels.

3. Wafer Processing
Patterning
 The series of processes that shape or alter the existing
shape of the deposited materials and is generally referred
to as lithography.
 For example, in conventional lithography, the wafer is
coated with a chemical called a photoresist. The
photoresist is exposed by a stepper, a machine that
focuses, aligns, and moves the mask, exposing select
portions of the wafer to short wavelength light.
 The unexposed regions are washed away by a developer
solution. After etching or other processing, the remaining
photoresist is removed by plasma ashing.
Modification of electrical properties
 Historically consisted of doping transistor sources and
drains originally by diffusion furnaces and later by ion
implantation.
 These doping processes are followed by furnace anneal
or in advanced devices, by rapid thermal anneal (RTA)
which serve to activate the implanted dopants.
 Modification of electrical properties now also extends to
reduction of dielectric constant in low-k insulating
materials via exposure to ultraviolet light in UV
processing (UVP).

4. Wafer Processing
FEOL
FEOL processing
 The formation of the transistors directly in the silicon. The raw wafer is engineered by
the growth of an ultrapure, virtually defect-free silicon layer through epitaxy.
 In the most advanced logic devices, prior to the silicon epitaxy step, tricks are performed
to improve the performance of the transistors to be built.
 One method involves introducing a straining step wherein a silicon variant such as
silicon-germanium (SiGe) is deposited. Once the epitaxial silicon is deposited, the crystal
lattice becomes stretched somewhat, resulting in improved electronic mobility.
 Another method, called silicon on insulator technology involves the insertion of an
insulating layer between the raw silicon wafer and the thin layer of subsequent silicon
epitaxy. This method results in the creation of transistors with reduced parasitic effects.
Gate oxide and implants
 Front-end surface engineering is followed by: growth of the gate dielectric, traditionally
silicon dioxide (SiO2), patterning of the gate, patterning of the source and drain regions,
and subsequent implantation or diffusion of dopants to obtain the desired
complementary electrical properties.
 In dynamic random access memory (DRAM) devices, storage capacitors are also
fabricated at this time, typically stacked above the access transistor.

5. Wafer Processing
BEOL
Metal Layers
 Once the various semiconductor devices
have been created, they must be
interconnected to form the desired
electrical circuits.
 This occurs in a series of wafer processing
steps collectively referred to as BEOL (not
to be confused with back end of chip
fabrication which refers to the packaging
and testing stages).
 BEOL processing involves creating metal
interconnecting wires that are isolated by
dielectric layers.
 The insulating material was traditionally a
form of SiO2 or a silicate glass, but recently
new low dielectric constant materials are
being used.
 These dielectrics presently take the form of
SiOC and have dielectric constants around
2.7 (compared to 3.9 for SiO2), although
materials with constants as low as 2.2 are
being offered to chipmakers.

6. Wafer Processing
BEOL
Interconnect
 Synthetic detail of a standard cell through
four layers of planarized copper
interconnect, down to the polysilicon, wells
and substrate.
 More recently, as the number of
interconnect levels for logic has
substantially increased due to the large
number of transistors that are now
interconnected in a modern chip, the
timing delay in the wiring has become
significant prompting a change in wiring
material from aluminium to copper and
from the silicon dioxides to newer low-K
material.
 As the number of interconnect levels
increases, planarization of the previous
layers is required to ensure a flat surface
prior to subsequent lithography. Without it,
the levels would become increasingly
crooked and extend outside the depth of
focus of available lithography, interfering
with the ability to pattern.

7. Processing – Prototyping
There are two methods of prototyping;
The first silicon MPW |MLM
Multi Product Wafer (MPW)
 Shared silicon technology for the
parallel processing of several devices
on one wafer
 Delivery of dies or ceramic samples
Benefits:
 Development charges
significantly reduced
Disadvantages:
 Fixed start dates and lead
times
 Only a small number of
untested samples available
 No volume production with
these masks

8. Processing – Prototyping
There are two methods of prototyping;
The first silicon MPW |MLM
Multi Level Mask (MLM)
 4 mask levels drawn on the same reticule
 Mask costs reduced down to 1/4 for all
technology nodes
Benefits:
 Flexible tape-in dates
 Start-stop options and design
revisions possible
Disadvantages:
 No volume production with
these masks

9. Processing
Wafer Thinning
Wafer Thinning
 A semiconductor device fabrication step
during which wafer thickness is reduced to
allow for stacking and high density
packaging of integrated circuits (IC).
 ICs are being produced on semiconductor
wafers that undergo a multitude of
processing steps. The silicon wafers
predominantly being used today have
diameters of 20 and 30 cm. They are
roughly 750 μm thick to ensure a minimum
of mechanical stability and to avoid warping
during high-temperature processing steps.
 The backside of the wafers are ground prior
to wafer dicing (where the individual
microchips are being singulated). Wafers
thinned down to 75 to 50 μm are common
today.
The process is also known as ‘Backlap’ or
'Wafer backgrinding‘.

10. Processing
Wafer Dicing
Wafer Dicing
 The process by which die are separated from a wafer
of semiconductor following the processing of the
wafer. The dicing process can be accomplished by
scribing and breaking, by mechanical sawing
(normally with a machine called a dicing saw) or by
laser cutting. Following the dicing process the
individual silicon chips are encapsulated into chip
carriers .
 During dicing, wafers are typically mounted on dicing
tape which has a sticky backing that holds the wafer
on a thin sheet metal frame. Once a wafer has been
diced, the pieces left on the dicing tape are referred
to as die, dice or dies. These will be packaged in a
suitable package or placed directly on a printed
circuit board substrate as a "bare die". The area that
has been cut away are called die streets which are
typically about 75 micrometres (0.003 inch) wide.
 The die created may be any shape generated by
straight lines, but they are typically rectangular or
square shaped.

1. Packaging
Development
Early Flat Packs
The earliest integrated circuits were packaged in ceramic flat packs, which continued to be used by the military
for their reliability and small size for many years. Commercial circuit packaging quickly moved to the dual in-line
package (DIP), first in ceramic and later in plastic
PGA & LCC
In the 1980s pin counts of VLSI circuits exceeded the practical limit for DIP packaging, leading to pin grid array
(PGA) and leadless chip carrier (LCC) packages. Surface mount packaging appeared in the early 1980s and
became popular in the late 1980s, using finer lead pitch with leads formed as either gull-wing or J-lead, as
exemplified by small-outline integrated circuit — a carrier which occupies an area about 30 – 50% less than an
equivalent DIP, with a typical thickness that is 70% less.
This package has "gull wing" leads protruding from the two long sides
and a lead spacing of 0.050 inches.
Small Outline Integrated Circuits
Small-outline integrated circuit (SOIC) and Plastic leaded
chip carrier (PLCC) packages. In the late 1990s,
plastic quad flat pack (PQFP) and thin small-outline packages (TSOP)
became the most common for high pin count devices,
though PGA packages are still often used for high-end microprocessors.

2. Packaging
BGD | SiP
Ball grid array (BGA) packages
 Have existed since the 1970s. Flip-chip Ball
Grid Array packages, which allow for much
higher pin count than other package types,
were developed in the 1990s.
 In an FCBGA package the die is mounted
upside-down (flipped) and connects to the
package balls via a package substrate that is
similar to a printed-circuit board rather
than by wires.
 FCBGA packages allow an array of input-
output signals (called Area-I/O) to be
distributed over the entire die rather than
being confined to the die periphery.
System in a Package (SiP)
 When multiple dies are stacked in one
package, it is called SiP, for System In
Package, or three-dimensional integrated
circuit.
 When multiple dies are combined on a
small substrate, often ceramic, it's called an
MCM, or Multi-Chip Module.

3. Packaging
QFN Part 1
QFN
 Flat no-leads packages such as QFN (quad-flat
no-leads) and DFN (dual-flat no-leads)
physically and electrically connect integrated
circuits to printed circuit boards. Flat no-leads,
also known as MicroLead Frame, is a surface-
mount technology, one of several package
technologies that connect ICs to the surfaces
of PCBs without through-holes.
 Flat no-lead is a near chip scale package
plastic encapsulated package made with a
planar copper lead frame substrate.
Perimeter lands on the package bottom
provide electrical connections to the PCB.
 Flat no-lead packages include an exposed
thermal pad to improve heat transfer out
of the IC (into the PCB). Heat transfer can
be further facilitated by metal vias in the
thermal pad.
The QFN package is similar to the quad-flat
package, and a ball grid array.

4. Packaging
QFN Part 2
QFN packages
 Two types of QFN packages are common: air-
cavity QFNs, with an air cavity designed into
the package, and plastic-moulded QFNs with
air in the package minimized.
Plastic Moulded QFN
 Less-expensive plastic-moulded QFNs usually
limited to applications up to ~2–3 GHz.
 It is usually composed of just 2 parts, a
plastic compound and copper lead frame,
and does not come with a lid.
Air-cavity QFN
 In contrast, the air-cavity QFN is usually made
up of 3 parts; a copper lead frame, plastic-
moulded body (open, and not sealed), and
either a ceramic or plastic lid.
 It is usually more expensive due to its
construction, and can be used for microwave
applications up to 20–25 GHz.
QFN packages can have a single row of contacts or a
double row of contacts.

5. Packaging
Flip Chip
Flip chip | C4
 Flip chip, also known as Controlled Collapse
Chip Connection or its acronym, C4, is a
method for interconnecting semiconductor
devices, such as IC chips and
Microelectromechanical systems (MEMS),
to external circuitry with solder bumps that
have been deposited onto the chip pads.
 The solder bumps are deposited on the
chip pads on the top side of the wafer
during the final wafer processing step. In
order to mount the chip to external
circuitry (e.g., a circuit board or another
chip or wafer), it is flipped over so that
its top side faces down, and aligned so
that its pads align with matching pads on
the external circuit, and then the solder
is flowed to complete the interconnect.
 This is in contrast to wire bonding, in
which the chip is mounted upright and
wires are used to interconnect the chip
pads to external circuitry.

6. Packaging
Flip Chip Process
Mounted chip is “under-filled” using an
electrically-insulating adhesive
Solder balls are then re-melted (typically using
hot air reflow)
Chips are flipped and positioned so that the
solder balls are facing
the connectors on the external circuitry
Chips are cut
Solder dots are deposited on each
of the pads
Pads are metalized on the surface
of the chips
Integrated circuits are created on the wafer

ASIC Initial Evaluation
Joint Evaluation
 Device evaluation is conducted by both the
SWINDON design team and also the customer.
 The design team will evaluate the device as a
stand alone component and the customer will
evaluate the device within it’s system.
 It is preferably conducted on identical
evaluation boards and set up in order to be
able to accurately correlate results.
Initial evaluation: -
 Power up.
 Turn on the power supply and check the
mains fuse has not blown, if not check current
consumption in key modes.
 Check functionality either, optimistically,
everything at once or block by block then a
full functional test.
 Look at the performance aspects (accuracy,
speed, settling time etc.) that are key
performance aspects to the chip for a few
samples at room temperature..

ASIC Full Evaluation
Functional and Parametric
 Once the initial checking has been
completed then a full evaluation (functional
and parametric) against the specification is
then carried out.
 This is conducted over the environmental
window (temperature and voltage), over a
limited number of samples (5 to 10), all
according to the evaluation schedule. T
 his schedule should be in existence well
before the initial prototype chips arrive at
the respective companies.
Parallel Testing
 In parallel samples will go to the test
department so that ATE development can
proceed.
 This will need a large number of samples to
be tested to ensure that the functional and
parametric yield is up to expectation.

ASIC Test Development
Part 1
The Test Development phase
Consists of developing the tests for the state of the art
ASICs. It is conducted in close co-operation with the
design team to develop DFT strategies, test methods,
verify test structures through simulation and generate
test vectors.
This phase covers the following areas:
1. Structural tests - Develop test vectors for
ATPG/JTAG/IDDQ.
2. Memory Tests - Develop test vectors for
embedded memories.
3. Develop tools to support Failure analysis
and Yield enhancement teams to physically
located failure locations on the chip.
4. Mixed-signal tests - Develop test vectors
for on-chip PLLs, DACs, ADCs, and other
analog/RF blocks.
5. Functional tests - Develop broadside
functional/Fmax test vectors for embedded
controllers and DSP cores.
6. Behavioural Modelling - Develop analog
models (DAC, ADC, PLL, up/down
converters and amplifiers) for pre-silicon
verification and test vector generation.

Part 2
Automatic Test Equipment (ATE )
 The aim is for the implementation of
these test vectors and methodologies
on Automatic Test Equipment (ATE)
during first silicon debug,
characterization, and production.
 The required skills to perform this
critical function includes;
 Strong knowledge of DFT: ATPG,
JTAG, IDDQ, At-speed ATPG, fault
simulation, fault analysis.
 Knowledge of Iddq test
techniques and At-speed ATPG
including transition and path delay
 Strong knowledge of test bench
development, simulation debug,
behavioural model development.

Results
Bespoke Test Regime
The results of this work in a bespoke test
regime for the ASIC under test and
includes;
 Fully automated wafer
and package level test
 Fully automated, online
test and QA procedures
 100% wafer level test,
each device
 100% package level test,
each package
 Real-time yield statistics
 Wafer and package level
tests correlated
 100% Datalog, each device
 Tri temperature test
 PPM field failure rate sub 1ppm

ASIC Production
The production of the ASIC comprises
many aspects of are that have already been covered.
1. Production Acceptance Review
 Prototypes are reviewed for
Production Suitability
2. Wafer Fabrication
 Production Orders from Silicon
Fabricator
3. Wafer Probe
 Die are tested at wafer level at CSS
 Test Program is Custom Made for
your ASIC
 Key Product Characteristics (KPC's)
are collected for Statistical Process
Control
4. Packaging
 A wide variety of packages are
available, as well as die delivery
5. Package Testing
 Packages are typically tested at CSS
 Test Program is Custom Made
 Delivery in rails, tape & reel or
waffle packs (die)
6. Production Reports
 Probe and Package Test Data is
analysed by Quality Engineering
and
 Yield and Statistical Process Control
information is available to ASIC
customers.
7. Order Fulfilment and Logistics
Forecasting
 Supply Chain Management
 Support functions

It is hugely preferential if your ASIC supplier has many of the fulfilment and logistics
capabilities in house. This will provide a much more risk averse supply chain and
SWINDON offers the complete service. From forecasting to shipping…
Forecasting
Supply Chain
Management Manufacturing
Warehousing
/ Shipping
Order
Management
Fulfilment and Logistics
In-house capabilities

The support functions that your ASIC supplier provides can be critical in order for your
company to perform to its highest level. SWINDON offers the highest support….
Environmental
Health and Safety
Warranty and
Returns
Financials
Resource
Management
Operations
Support
Fulfilment and Logistics
Support Functions

10 Reasons why…
SWINDON makes a good choice
for your next ASIC project
Design and productionisation expertise
Gained over 30 years of successful projects
Fixed development costs and unit prices
Design ownership
Production supply
In house wafer probe and ATE production test
Lifetime product support
Financial stability
Quality
Partnership Approach

Any questions?
 We have a full range of resources from case histories to
planning checklists
 Please visit our web site www.swindonsilicon.co.uk
Headquarters & Design Centre
Swindon Silicon Systems Limited
Radnor Street
Swindon Wiltshire SN1 3PR
United Kingdom
Tel: +44 (0) 1793 649400
email: sales@swindonsilicon.co.uk

Making of an Application Specific Integrated Circuit

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