Timing Diagram of MVI Instruction of 8085 Microprocessor

Name: Dhrumil I. Panchal
Subject: Microprocessor and Interfacing
Branch: Computer Engineering (B.E.)
Year: 2019-20

Instruction cycle(Bus timing diagram) of MVI B, 05H

MVI Instruction
Timing Diagram
Opcode Fetch Cycle
Memory Read Cycle
Frequency

It stores the immediate 8 bit data to a register
or memory location.
Example: MVI B, 05H
Opcode: MVI
Operand: B is the destination register and 05
is the source data which needs to be
transferred to the register.
‘05’ data is stored in the B register.

 Here, opcode is ‘MVI B’ and data is 05.
 Assume the memory address of the opcode and
the data. For example: MVI B, 05
2000: Opcode
2001: 45
 The opcode fetch will be same in all the
instructions.
 Only the read instruction of the opcode needs to
be added in the successive T states.
 For the opcode read the IO/M (low active) = 0,
S1 = 1 and S0 = 0. Also, only 3 T states will be
required.

Timing Diagram of MVI Instruction of 8085 Microprocessor

 00 – lower bit of address where opcode is stored, i.e.,
00
 20 – higher bit of address where opcode is stored,
i.e., 20.
 ALE – Provides signal for multiplexed address and
data bus.
 Only in t1 it used as address bus to fetch lower bit of
address otherwise it will be used as data bus.
 RD (low active) – Signal is 1 in t1, t2 & t4, no data is
read by microprocessor. Signal is 0 in t3, data is read
by microprocessor.
 WR (low active) – Signal is 1 throughout, no data is
written by microprocessor.
 IO/M (low active), S0 and S1 – Signal is 1 in
throughout, operation is performing on input/output.

 00 – lower bit of address where opcode is stored, i.e, 01
 20 – higher bit of address where opcode is stored, i.e, 20.
 ALE – Provides signal for multiplexed address and data
bus. Only in t5 it used as address bus to fetch lower bit of
address otherwise it will be used as data bus.
 RD (low active) – Signal is 1 in t1, t2 & t4, no data is read
by microprocessor. Signal is 0 in t3, data is read by
microprocessor.
 WR (low active) – Signal is 1 throughout, no data is
written by microprocessor.
 IO/M (low active) and S1 – Signal is 1 in throughout,
operation is performing on input/output.
S0 – Signal is 0 throughout, operation is performing on
memory.

Assume that the clock Frequency = 2 MHz
T state = clock period = (1/f) = 0.5 us
Execution Time for
Opcode Fetch = 4*T = 2 us
Memory Read = 3*T = 1.5 us
Total Time = 2+1.5 = 3.5 us

Inspiration from Prof. Parul Bakaraniya
Notes of MI
Book of MI (By Gaonkar)
Images from Google Images
Some My Own Knowledge

Timing Diagram of MVI Instruction of 8085 Microprocessor

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Timing Diagram of MVI Instruction of 8085 Microprocessor