This document provides a summary of an industrial project on a four way traffic control system implemented using an FPGA. The project was completed by Ameesha Singh and Chetan Dabral for their Bachelor of Technology degree in Electronics and Communication Engineering from Mahatma Gandhi Mission's College of Engineering and Technology, affiliated with Dr. A.P.J. Abdul Kalam Technical University. The project aims to design a traffic light controller using Verilog HDL that can manage traffic flow at a four road intersection through sequencing the red, yellow, and green lights. Xilinx ISE Project Navigator and iSIM simulator were used for the design, simulation, and testing of the traffic light controller system implemented on an FPGA