Transformer vector group_test_conditions

Transformer vector group_test_conditions

• 1.
  Test Conditions forvarious vector groups commonly under use are listed along with pictorial representation. Assuming the reader has sufficient exposure to transformer winding connections. Transformer Vector Group Test conditions YNd1, YNd11, Dyn11, YNyn0 and more Pandian
• 2.
  Transformer Vector GroupTest conditions 1. Ensure only one terminal of HV and one terminal of LV is connected together 2. Ensure the additive voltage does not exceeds the safe limit Page 1 Index Chapter Page Cover page Index 1 Introduction about Vector Group Notation 2 Test Conditions for Ii0 & Ii6 3 Test Conditions for YNyn0 4 Test Conditions for YNyn6 5 Test Conditions for Dd0 7 Test Conditions for Dd6 8 Test Conditions for YNd1 10 Test Conditions for YNd11 11 Test Conditions for Dyn11 12 Test Conditions for Dyn1 13
• 3.
  Transformer Vector GroupTest conditions 1. Ensure only one terminal of HV and one terminal of LV is connected together 2. Ensure the additive voltage does not exceeds the safe limit Page 2 Introduction In transformers the interconnection of the coils and the phase angle between the primary and secondary side are denoted by standard form. Transformers with similar connections and phase shift are grouped under a Vector group. Standard notations to denote the connection are listed below Connection Notation HV Winding Star Y Delta D Neutral N Zig Zag Z Single Phase I LV Winding Star y Delta d Zig Zag z Neutral n Single Phase i The phase shift between the primary and secondary side are denoted in the form of Clock Position. Taking HV side as the reference (i.e. 12 o Clock position) phase shift of the LV side is mentioned in numerical values in multiples of 30° 0 denotes 0°, 1 denotes 30°, 6 denotes 180° and so on. In special transformer where the phase shift is not in multiples of 30° particularly for the isolation transformer incorporated to reduce the harmonics, directly the phase angle is been mentioned by the manufacturers To carry out the Vector Group test one should establish the electrical connection between Primary and Secondary since the separate winding transformers are inductively coupled whereas the auto transformers are electrically coupled and so no need for latter. After establishing the electrical connection between two windings under test, voltage may be applied in either of the winding preferably in the HV side as it is safe and the voltage measured between the various terminals will be indicative to ensure the phase shift. Testing Engineer should derive at least three conditions to compare, add and or equate the particular set of voltage to be measured. These conditions should be in such way to ensure the phase shift and phase sequence. Usually 1U and 2u are connected but it is not necessarily to be so, Testing Engineer can choose by his/her own choice and the conditions shall be derived accordingly. If the derived conditions are satisfied the vector shall be confirmed.
• 4.
  Transformer Vector GroupTest conditions 1. Ensure only one terminal of HV and one terminal of LV is connected together 2. Ensure the additive voltage does not exceeds the safe limit Page 3 Ii0 Connect 1P and 2p Keep the neutral(1N & 2n)l floating Apply Voltage in HV side Condition Measure Voltage between 1. 1P and 2n (V1P2n ) 2. 2n and 1N (V2n1N ) 3. 1P and 1N (V1P1N ) V1P2n + V2n1N = V1P1N Ii6 Connect 1P and 2p Keep the neutral(1N & 2n)l floating Apply Voltage in HV side Condition Measure Voltage between 1. 1P and 2n (V1P2n ) 2. 2n and 1N (V2n1N ) 3. 1P and 1N (V1P1N ) V1P2n + V1P1N = V2n1N V1P1N V2n1N V1P2n 1P & 2p 2n 1N 1N 1P 2p 2n 1N 1P 2n 2p V1P2n V1P1N V1N2n 1P & 2p 2n 1N
• 5.
  Transformer Vector GroupTest conditions 1. Ensure only one terminal of HV and one terminal of LV is connected together 2. Ensure the additive voltage does not exceeds the safe limit Page 4 YNyn0 Connect 1U and 2u Keep the neutral floating Apply 3Φ Voltage in HV side Condition – 1 Measure Voltage between 1. 1U and 2n (V1U2n ) 2. 2n and 1N (V2n1N ) 3. 1U and 1N (V1U1N ) V1U2n + V2n1N = V1U1N Condition – 2 Measure Voltage between 1. 1W and 2w ( V1W2w ) 2. 1V and 2v (V1V2v ) V1W2w = V1V2v Condition – 3 Measure Voltage between 1. 1W and 2w (V1W2w ) 2. 1W and 2v (V1V2v ) V1W2w < V1w2v V1W2w 2n 2w 2v 1U&2u 1W 1V 1N V1W2v 1U 1W 1V 1N 2u 2w 2v 2n V2n1N V1U2n V1U1N 2n 2w 2v 1U&2u 1W 1V 1N V1V2v V1W2w 2n 2w 2v 1U&2u 1W 1V 1N
• 6.
  Transformer Vector GroupTest conditions 1. Ensure only one terminal of HV and one terminal of LV is connected together 2. Ensure the additive voltage does not exceeds the safe limit Page 5 YNyn6 Connect 1U and 2u Keep the neutral floating Apply 3Φ Voltage in HV side Condition – 1 Measure Voltage between 1. 1U and 2n (V2n1U ) 2. 2n and 1N (V2n1N ) 3. 1U and 1N (V1U1N ) V2n1U + V1U1N = V2n1N Condition – 2 Measure Voltage between 1. 1W and 2v ( V1W2v ) 2. 1V and 2w (V1V2w ) V1W2v = V1V2w 1U 1W 1V 1N 2u 2w 2v 2n V1V2w V1W2v 1U& 2u 1W 1V 1N 2w 2v 2n V2n1N V2n1U V1U1N 1U& 2u 1W 1V 1N 2w 2v 2n
• 7.
  Transformer Vector GroupTest conditions 1. Ensure only one terminal of HV and one terminal of LV is connected together 2. Ensure the additive voltage does not exceeds the safe limit Page 6 YNyn6…(contd) Condition – 3 Measure Voltage between 1. 1W and 2v (V1W2v ) 2. 1W and 2w (V1w2w ) V1W2w > V1w2v *By connecting 1U and 2u the Voltage V1W2w may be high, hence the author feels comfortable to connect 1U and 2n. Then the Condition – 1 changes as follows and the Conditions – 2 & 3 remains unchanged Measure Voltage between 1. 1U and 2u (V1U2u ) 2. 2u and 1N (V2u1N ) 3. 1U and 1N (V1U1N ) V1U2u + V2u1N = V1U1N V1W2w V1W2v 1U& 2u 1W 1V 1N 2w 2v 2n V2u1N V1W2w V1U2u 1U& 2n 1W 1V 1N 2w 2v 2u
• 8.
  Transformer Vector GroupTest conditions 1. Ensure only one terminal of HV and one terminal of LV is connected together 2. Ensure the additive voltage does not exceeds the safe limit Page 7 Dd0 Connect 1U and 2u Apply 3Φ Voltage in HV side Condition – 1 Measure Voltage between 1. 1U and 2w (V1U2w ) 2. 2w and 1W (V2w1W ) 3. 1U and 1W (V1U1W ) V1U2w + V2w1W = V1U1W Condition – 2 Measure Voltage between 1. 1U and 2v (V1U2v ) 2. 2v and 1V (V2v1V ) 3. 1U and 1V (V1U1V ) V1U2v + V2v1V = V1U1V Condition – 3 Measure Voltage between 1. 1W and 2v (V1W2v ) 2. 1W and 2w (V1w2w ) V1W2w < V1w2v 1W 1V 1U 2w 2v 2u 2w 2v 1U&2u 1W 1V 2v 2w 1U&2u 1V 1W 2w 2v 1U&2u 1W 1V V1W2v
• 9.
  Transformer Vector GroupTest conditions 1. Ensure only one terminal of HV and one terminal of LV is connected together 2. Ensure the additive voltage does not exceeds the safe limit Page 8 Dd6 Connect 1U and 2u Apply 3Φ Voltage in HV side Condition – 1 Measure Voltage between 1. 1U and 2w (V1U2w ) 2. 2w and 1W (V1W2w ) 3. 1U and 1W (V1U1W ) V1U1W + V1U2w = V1W2w Condition – 2 Measure Voltage between 1. 1U and 2v (V1U2v ) 2. 2v and 1V (V1V2v ) 3. 1U and 1V (V1U1V ) V1U1V + V1U2v = V1V2v 1W 1V 1U 2w 2v 2u 1V 1W 1U&2u 2v 2w V1V2v V1U2v 1W 1V 1U&2u 2w 2v V1W2w V1U2w
• 10.
  Transformer Vector GroupTest conditions 1. Ensure only one terminal of HV and one terminal of LV is connected together 2. Ensure the additive voltage does not exceeds the safe limit Page 9 Dd6…(contd) Condition – 3 Measure Voltage between 1. 1W and 2v (V1W2v ) 2. 1W and 2w (V1w2w ) V1W2w > V1w2v *By connecting 1U and 2u the Voltage V1W2w may be high, hence the author feels comfortable to connect 1U and 2v and conditions shall be derived accordingly. 1W 1V 1U&2u 2w 2v V1W2w
• 11.
  Transformer Vector GroupTest conditions 1. Ensure only one terminal of HV and one terminal of LV is connected together 2. Ensure the additive voltage does not exceeds the safe limit Page 10 YNd1 Connect 1U and 2u Keep the neutral floating Apply 3Φ Voltage in HV side Condition - 1 Measure Voltage between 1. 1U and 2v (V1U2v ) 2. 2v and 1N (V2v1N ) 3. 1U and 1N (V1U1N ) V1U2v + V2v1N = V1U1N Condition – 2 Measure Voltage between 1. 1W and 2w ( V1W2w ) 2. 1V and 2w (V1V2w ) V1W2w < V1V2w Condition – 3 Measure Voltage between 1. 1W and 2v (V1W2V ) 2. 1V and 2v (V1V2v ) V1W2V = V1V2v 1U 1W 1V 1N 2v 2u 2w V1U1N V2v1N V1U2v 1U & 2u 2w 2v 1N 1V 1W V1V2w V1W2w 1U & 2u 2w 2v 1N 1V 1W V1W2v V1V2v 1U & 2u 2w 2v 1N 1V 1W
• 12.
  Transformer Vector GroupTest conditions 1. Ensure only one terminal of HV and one terminal of LV is connected together 2. Ensure the additive voltage does not exceeds the safe limit Page 11 YNd11 Connect 1U and 2u Keep the neutral floating Apply 3Φ Voltage in HV side Condition - 1 Measure Voltage between 1. 1U and 2w (V1U2w ) 2. 2w and 1N (V2w1N ) 3. 1U and 1N (V1U1N ) V1U2w + V2w1N = V1U1N Condition - 2 Measure Voltage between 1. 1W and 2v ( V1W2v ) 2. 1V and 2v (V1V2v ) V1W2v > V1V2v Condition -3 Measure Voltage between 1. 1W and 2w (V1W2w ) 2. 1V and 2w (V1V2w ) V1W2w = V1V2w V1V2w V1W2w V1V2v V1W2v V1U1N V1U2w V2w1N 1U 1W 1V 1N 2v 2u 2w 1U & 2u 1W 1V 1N 2w 2v 1U & 2u 1W 1V 1N 2w 2v 1U & 2u 1W 1V 1N 2w 2v
• 13.
  Transformer Vector GroupTest conditions 1. Ensure only one terminal of HV and one terminal of LV is connected together 2. Ensure the additive voltage does not exceeds the safe limit Page 12 Dyn11 Connect 1U and 2u Keep the neutral floating Apply 3Φ Voltage in HV side Condition - 1 Measure Voltage between 1. 1U and 2n (V1U2n ) 2. 2n and 1V (V2n1V ) 3. 1U and 1V (V1U1V ) V1U2n + V2n1V = V1U1V Condition - 2 Measure Voltage between 1. 1W and 2v ( V1W2v ) 2. 1W and 2w (V1W2w ) V1W2v > V1W2w Condition -3 Measure Voltage between 1. 1V and 2v (V1V2v ) 2. 1V and 2w (V1V2w ) V1V2v = V1V2w 1W 1V 1U 2n 2w 2v 2u V2n1V V1U1V V1U2n 2n 2w 2v 1W 1V 1U& 2u 2n 2w 2v 1W 1V 1U& 2u V1W2v 2w 2n 2v 1W 1V 1U& 2u V1W2w
• 14.
  Transformer Vector GroupTest conditions 1. Ensure only one terminal of HV and one terminal of LV is connected together 2. Ensure the additive voltage does not exceeds the safe limit Page 13 Dyn1 Connect 1U and 2u Keep the neutral floating Apply 3Φ Voltage in HV side Condition - 1 Measure Voltage between 1. 1U and 2n (V1U2n ) 2. 2n and 1W (V2n1W ) 3. 1U and 1W (V1U1W ) V1U2n + V2n1W = V1U1W Condition - 2 Measure Voltage between 1. 1V and 2v ( V1V2v ) 2. 1V and 2w (V1V2w ) V1V2w > V1V2v Condition -3 Measure Voltage between 1. 1W and 2v (V1W2v ) 2. 1W and 2w (V1W2w ) V1W2v = V1W2w 1W 1V 1U 2n 2w 2v 2u V1U1W V2n1W 2n 2w 2v 1W 1V 1U&2u V1U2n V1V2w 2n 2w 2v 1W 1V 1U&2u V1V2v V1V2v V1V2w 2n 2w 2v 1W 1V 1U&2u