Unit 4

Unit 4

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  NEC-409: ANALOG ANDDIGITAL ELECTRONICS MCQ for unit 4 1. A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register. A. 1 B. 2 C. 4 D. 8 2. In a sequential circuit the next state is determined by ________ and _______. A. State variable, current state B. Current state, flip-flop output C. Current state and external input D. Input and clock signal applied 3. The divide-by-60 counter in digital clock is implemented by using two cascading counters: A. Mod-6, Mod-10 B. Mod-50, Mod-10 C. Mod-10, Mod-50 D. Mod-50, Mod-6 4. The minimum time for which the input signal has to be maintained at the input of flipflop is called ______ of the flip-flop. A. Set-up time B. Hold time C. Pulse Interval time D. Pulse Stability time (PST) 5. ____________ is said to occur when multiple internal variables change due to change in one input variable. A. Clock Skew B. Race condition C. Hold delay D. Hold and Wait 6. The _____________ input overrides the ________ input. A. Asynchronous, synchronous B. Synchronous, asynchronous C. Preset input (PRE), Clear input (CLR) D. Clear input (CLR), Preset input (PRE) 7. A decade counter is __________. A. Mod-3 counter B. Mod-5 counter C. Mod-8 counter
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  D. Mod-10 counter 8.In asynchronous transmission when the transmission line is idle, _________. A. It is set to logic low B. It is set to logic high C. Remains in previous state D. State of transmission line is not used to start transmission 9. A Nibble consists of _____ bits. A. 2 B. 4 C. 8 D. 16 10. The voltage gain of the Inverting Amplifier is given by the relation ________ . A. Vout / Vin = - Rf / Ri B. Vout / Rf = - Vin / Ri C. Rf / Vin = - Ri / Vout D. Rf / Vin = Ri / Vout 11. LUT is acronym for _________ . A. Look Up Table B. Local User Terminal C. Least Upper Time Period D. None of given options 12. The three fundamental gates are ___________. A. AND, NAND, XOR B. OR, AND, NAND C. NOT, NOR, XOR D. NOT, OR, AND 13. The total amount of memory that is supported by any digital system depends upon ______. A. The organization of memory B. The structure of memory C. The size of decoding unit D. The size of the address bus of the microprocessor 14. Stack is an acronym for _________ . A FIFO memory B. LIFO memory C. Flash Memory D. Bust Flash Memory 15. ___________ is one of the examples of synchronous inputs. A. J-K input B. EN input C. Preset input (PRE) D. Clear Input (CLR) 16. In a state diagram, the transition from a current state to the next state is determined by: A. Current state and the inputs B. Current state and outputs
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  C. Previous stateand inputs D. Previous state and outputs 17. ________ is used to simplify the circuit that determines the next state. A. State diagram B. Next state table C. State reduction D. State assignment 18. A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register. A. 1 B. 2 C. 4 D. 8 19. The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________. A. Doesn’t have an invalid state B. Sets to clear when both J = 0 and K = 0 C. It does not show transition on change in pulse D. It does not accept asynchronous inputs 20. A positive edge-triggered flip-flop changes its state when ________________ . A. Low-to-high transition of clock B. High-to-low transition of clock C. Enable input (EN) is set D. Preset input (PRE) is set 21. In a sequential circuit the next state is determined by ________ and _______. A. State variable, current state B. Current state, flip-flop output C. Current state and external input D. Input and clock signal applied 22. The divide-by-60 counter in digital clock is implemented by using two cascading counters: A. Mod-6, Mod-10 B. Mod-50, Mod-10 C. Mod-10, Mod-50 D. Mod-50, Mod-6 23. Flip flops are also called _____________. A. Bi-stable dualvibrators B. Bi-stable transformer C. Bi-stable multivibrators D. Bi-stable singlevibrators 24. The minimum time for which the input signal has to be maintained at the input of flipflop is called ______ of the flip-flop. A. Set-up time B. Hold time C. Pulse Interval time D. Pulse Stability time (PST) 25. A decade counter is __________.
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  A. Mod-3 counter B.Mod-5 counter C. Mod-8 counter D. Mod-10 counter 26. DRAM stands for __________. A. Dynamic RAM B. Data RAM C. Demoduler RAM D.None of above 27. The expression F=A+B+C describes the operation of three bits _____ Gate. A. OR B. AND C. NOT D. NAND 28. The decimal “17” in BCD will be represented as _________. A. 11101 B. 11011 C. 10111 D. 11110 29. The basic building block for a logical circuit is _______. A. A Flip-Flop B. A Logical Gate C. An Adder D. None of above 30. The output of the expression F=A.B.C will be Logic ________ when A=1, B=0, C=1. A. Undefined B. One C. Zero D. No Output as input is invalid