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Unit 4 Introduction to Microcontrollers.pptxUnit-3 IO Interfacing-1.pptximportant questions to be noted

The document provides a comprehensive overview of the 8051 microcontroller architecture, detailing its internal components such as the CPU, memory organization, I/O ports, and the instruction set. Key features include a 4KB ROM, 128 bytes of RAM, multiple timers, and various addressing modes and interrupt systems. The text also elaborates on the basic functions, pin configurations, and types of memory associated with the 8051 microcontroller.

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UNIT-IV: 8051 Microcontroller Architecture, I/O ports, register set, Memory organization, Addressing modes and Instruction set of 8051, Interrupts in 8051, Interrupt Priority in the 8051.
Intruduction • Microprocessor = CPU on a single chip. – ALU + registers + control +… • Micro-computer = small computer – uP + I/O + memory + peripheral + … • Microcontroller (uC) – u-Computer on a single chip of silicon
uP vs. uC  A uP  single-chip contained only CPU  bus is available  RAM capacity, num of port is selectable  RAM is larger than ROM (usually)  A uC  single-chip contained CPU, RAM, ROM, Prepherals, I/O port  Communicate by port  internal hardware is fixed  ROM is larger than RAM (usually)
8051 Basic Component • 4K bytes internal ROM • 128 bytes internal RAM • Four 8-bit I/O ports (P0 - P3). • Two 16-bit timers/counters • One serial interface RAM I/O Port Timer Serial COM Port Microcontroller CPU A single chip ROM
Block Diagram CPU Interrupt Control OSC Bus Control 4k ROM Timer 1 Timer 2 Serial 128 bytes RAM 4 I/O Ports TXD RXD External Interrupts P0 P2 P1 P3 Addr/Data
Other 8051 featurs • only 1 On chip oscillator (external crystal) • 6 interrupt sources (2 external , 3 internal, Reset) • 64K external code (program) memory(only read)PSEN • 64K external data memory(can be read and write) by RD,WR • Code memory is selectable by EA (internal or external) • We may have External memory as data and code
8051 Internal Block Diagram
8051 Foot Print 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (T0)P3.4 (T1)P3.5 XTAL2 XTAL1 GND (INT0)P3.2 (INT1)P3.3 (RD)P3.7 (WR)P3.6 Vcc P0.0(AD0 ) P0.1(AD1) P0.2(AD2 ) P0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14 ) P2.5(A13 ) P2.4(A12 ) P2.3(A11 ) P2.2(A10) P2.1(A9) P2.0(A8) 8051 (8031) (8751) (8951)
Important Pins • PSEN’ (out): Program Store Enable – Read for External Code Memory (active low) • ALE (out): Address Latch Enable – to latch address outputs at Port0 and Port2 • EA’ (in): External Access Enable – to access external program memory 0 to 4K (active low) • RXD,TXD: UART pins for serial I/O on Port 3 • Vcc （ pin 40 ） : +5V (3~5V for 89LV51) • GND （ pin 20 ） : ground • XTAL1 , XTAL2 （ pins 19,18 ） 9 • RST （ pin 9 ）： reset (active high)
Important Pins (IO Ports) • One of the most useful features = four I/O ports (P0 - P3) • Port 0 ： P0 （ P0.0 ～ P0.7 ） – 8-bit R/W - General Purpose I/O – low byte address and data bus for external memory • Port 1 ： P1 （ P1.0 ～ P1.7 ） – Only 8-bit R/W - General Purpose I/O • Port 2 ： P2 （ P2.0 ～ P2.7 ） – 8-bit R/W - General Purpose I/O – high byte address for external memory • Port 3 ： P3 （ P3.0 ～ P3.7 ） – General Purpose I/O – Timers(T0,T1) – ext. int (INT0, INT1) – Serial (TXD, RXD)- RD,WR • Each port can be used as input or output (bi-direction)
Port 3 Alternate Functions
Hardware Structure of I/O Pin D Q Clk Q Vcc Internal Pull-Up Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X B1 B2
Hardware Structure of I/O Pin • Each pin of I/O ports – Internally connected to CPU bus – A D latch store the value of this pin • Write to latch ＝ 1 ： write data into the D latch – 2 Tri-state buffer ： • B1: controlled by “Read pin” – Read pin ＝ 1 ： really read the data present at the pin • B2: controlled by “Read latch” – Read latch ＝ 1 ： read value from internal latch – A transistor M1 gate • Gate=0: open • Gate=1: close
Writing “1” to Output Pin P1.X D Q Clk Q Vcc Internal Pull-Up Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X 2. output pin is Vcc 1. write a 1 to the pin 1 0 output 1 B1 B2
Writing “0” to Output Pin P1.X D Q Clk Q Vcc Internal Pull-Up Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X 2. output pin is ground 1. write a 0 to the pin 0 1 output 0 B1 B2
Port3 Alternate IO 1
Types of Memory External DATA Memory ( up to 64KB ) RAM External CODE Memory ( up to 64KB ) ROM 8051 Chip 0000h FFFFh FFFFh Internal RAM SFRs Internal code Memory ( EEPROM ) 0000h
Types of Memory • External Code Memory (64k) • External RAM Data Memory (64k) • Internal Code Memory – 4k,8k,12k,20k – ROM, EPROM, EEPROM • Internal RAM – First 128 bytes: 00h to 1Fh Register Banks 20h to 2Fh Bit Addressable RAM 30 to 7Fh General Purpose RAM – Next 128 bytes: 80h to FFh Special Function Registers
External Memory • /EA （ pin 31 ）： external access – /EA=‘0’ indicates that code is stored externally. – /PSEN ＆ ALE are used for external ROM. – For 8051 internal code, /EA pin is connected to Vcc. – “/” means active low. • /PSEN （ pin 29 ）： program store enable – Output- connected to OE of ROM. – Read signal – fetch from ROM
External Memory • ALE （ pin 30 ） : address latch enable – It is an output pin and is active high – 8051 port 0 provides both address and data – The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.
On-Chip Memory Internal RAM
General Purpose Register 07 06 05 04 03 02 01 00 R7 R6 R5 R4 R3 R2 R1 R0 0F 08 17 10 1F 18 Bank 3 Bank 2 Bank 1 Bank 0 4 Register Banks Each bank has R0-R7 Selectable by PSW.2,3
Bit Addressable Memory 20h – 2Fh (16 locations  8-bits = 128 bits) 7F 78 1A 10 0F 08 07 06 05 04 03 02 01 00 27 26 25 24 23 22 21 20 2F 2E 2D 2C 2B 2A 29 28 Bit addressing: mov C, 1Ah or mov C, 23h.2
Special Function Registers DATA registers CONTROL registers Timers Serial ports Interrupt system Analog to Digital converter Digital to Analog converter Etc. Addresses 80h – FFh Direct Addressing used to access SFRs
Summary of on-chip data memory (RAM) MOV C, 67H ≡ MOV C, 2CH.7
Program Status Word (PSW)
8051 CPU Registers A (Accumulator) B PSW (Program Status Word) SP (Stack Pointer) PC (Program Counter) DPTR (Data Pointer) Used in assembler instructions
Registers A B R0 R1 R3 R4 R2 R5 R7 R6 DPH DPL PC DPTR PC Some 8051 16-bit Register Some 8-bit Registers of the 8051
Addressing Modes Immediate Mode – specify data by its value mov A, #0 ;put 0 in the accumulator ;A = 00000000 mov R4, #11h ;put 11hex in the R4 register ;R4 = 00010001 mov B, #11 ;put 11 decimal in b register ;B = 00001011 mov DPTR,#7521h ;put 7521 hex in DPTR ;DPTR = 0111010100100001
Addressing Modes Register Addressing – either source or destination is one of CPU register MOV R0,A MOV A,R7 ADD A,R4 ADD A,R7 MOV DPTR,#25F5H MOV R5,DPL MOV R,DPH Note that MOV R4,R7 is incorrect
Addressing Modes Direct Mode – specify data by its 8-bit address Usually for 30h-7Fh of RAM Mov a, 70h ; copy contents of RAM at 70h to a Mov R0,40h ; copy contents of RAM at 40h to R0 Mov 56h,a ; put contents of a at 56h to a Mov 0D0h,a ; put contents of a into PSW
Addressing Modes Register Indirect – the address of the source or destination is specified in registers Uses registers R0 or R1 for 8-bit address: mov psw, #0 ; use register bank 0 mov r0, #0x3C mov @r0, #3 ; memory at 3C gets #3 ; M[3C]  3 Uses DPTR register for 16-bit addresses: mov dptr, #0x9000 ; dptr  9000h movx a, @dptr ; a  M[9000] Note that 9000 is an address in external memory
Addressing Modes Register Indexed Mode – source or destination address is the sum of the base address and the accumulator(Index) • Base address can be DPTR or PC mov dptr, #4000h mov a, #5 movc a, @a + dptr ;a  M[4005]
The 8051 Assembly Language
Overview • Data transfer instructions • Addressing modes • Data processing (arithmetic and logic) • Program flow instructions
Data Transfer Instructions • MOV dest, source dest  source • Stack instructions PUSH byte ;increment stack pointer, ;move byte on stack POP byte ;move from stack to byte, ;decrement stack pointer • Exchange instructions XCH a, byte ;exchange accumulator and byte XCHD a, byte ;exchange low nibbles of ;accumulator and byte
Exchange Instructions two way data transfer XCH a, 30h ; a  M[30] XCH a, R0 ; a  R0 XCH a, @R0 ; a  M[R0] XCHD a, R0 ; exchange “digit” R0[7..4] R0[3..0] a[7..4] a[3..0] Only 4 bits exchanged
Data Processing Instructions Arithmetic Instructions Logic Instructions
Arithmetic Instructions • Add • Subtract • Increment • Decrement • Multiply • Divide • Decimal adjust
Arithmetic Instructions Mnemonic Description ADD A, byte add A to byte, put result in A ADDC A, byte add with carry SUBB A, byte subtract with borrow INC A increment A INC byte increment byte in memory INC DPTR increment data pointer DEC A decrement accumulator DEC byte decrement byte MUL AB multiply accumulator by b register DIV AB divide accumulator by b register DA A decimal adjust the accumulator
ADD Instructions add a, byte ; a  a + byte addc a, byte ; a  a + byte + C These instructions affect 3 bits in PSW: C = 1 if result of add is greater than FF AC = 1 if there is a carry out of bit 3 OV = 1 if there is a carry out of bit 7, but not from bit 6, or visa versa.
Instructions that Affect PSW bits
ADD Examples mov a, #3Fh add a, #D3h • What is the value of the C, AC, OV flags after the second instruction is executed? 0011 1111 1101 0011 10001 0010 C = 1 AC = 1 OV = 0
Signed Addition and Overflow 0111 1111 (positive 127) 0111 0011 (positive 115) 1111 0010 (overflow cannot represent 242 in 8 bits 2’s complement) 2’s complement: 0000 0000 00 0 … 0111 1111 7F 127 1000 0000 80 -128 … 1111 1111 FF -1 1000 1111 (negative 113) 1101 0011 (negative 45) 0110 0010 (overflow) 0011 1111 (positive) 1101 0011 (negative) 0001 0010 (never overflows)
Addition Example ; Computes Z = X + Y ; Adds values at locations 78h and 79h and puts them in 7Ah ;------------------------------------------------------------------ X equ 78h Y equ 79h Z equ 7Ah ;----------------------------------------------------------------- org 00h ljmp Main ;----------------------------------------------------------------- org 100h Main: mov a, X add a, Y mov Z, a end
Subtract SUBB A, byte subtract with borrow Example: SUBB A, #0x4F ;A  A – 4F – C Notice that There is no subtraction WITHOUT borrow. Therefore, if a subtraction without borrow is desired, it is necessary to clear the C flag. Example: Clr c SUBB A, #0x4F ;A  A – 4F
Increment and Decrement • The increment and decrement instructions do NOT affect the C flag. • Notice we can only INCREMENT the data pointer, not decrement. INC A increment A INC byte increment byte in memory INC DPTR increment data pointer DEC A decrement accumulator DEC byte decrement byte
Example: Increment 16-bit Word • Assume 16-bit word in R3:R2 mov a, r2 add a, #1 ; use add rather than increment to affect C mov r2, a mov a, r3 addc a, #0 ; add C to most significant byte mov r3, a
Multiply When multiplying two 8-bit numbers, the size of the maximum product is 16-bits FF x FF = FE01 (255 x 255 = 65025) MUL AB ; BA  A * B Note : B gets the High byte A gets the Low byte
Division • Integer Division DIV AB ; divide A by B A  Quotient(A/B) B  Remainder(A/B) OV - used to indicate a divide by zero condition. C – set to zero
Decimal Adjust DA a ; decimal adjust a Used to facilitate BCD addition. Adds “6” to either high or low nibble after an addition to create a valid BCD number. Example: mov a, #23h mov b, #29h add a, b ; a  23h + 29h = 4Ch (wanted 52) DA a ; a  a + 6 = 52
Logic Instructions  Bitwise logic operations  (AND, OR, XOR, NOT)  Clear  Rotate  Swap Logic instructions do NOT affect the flags in PSW
Bitwise Logic ANL  AND ORL  OR XRL  XOR CPL  Complement Examples: 00001111 10101100 ANL 00001111 10101100 ORL 00001111 10101100 XRL 10101100 CPL 00001100 10101111 10100011 01010011
Address Modes with Logic a, byte direct, reg. indirect, reg, immediate byte, a direct byte, #constant a ex: cpl a ANL – AND ORL – OR XRL – eXclusive oR CPL – Complement
Uses of Logic Instructions • Force individual bits low, without affecting other bits. anl PSW, #0xE7 ;PSW AND 11100111 • Force individual bits high. orl PSW, #0x18 ;PSW OR 00011000 • Complement individual bits xrl P1, #0x40 ;P1 XRL 01000000
Other Logic Instructions CLR - clear RL – rotate left RLC – rotate left through Carry RR – rotate right RRC – rotate right through Carry SWAP – swap accumulator nibbles
CLR ( Set all bits to 0) CLR A CLR byte (direct mode) CLR Ri (register mode) CLR @Ri (register indirect mode)
Rotate • Rotate instructions operate only on a RL a Mov a,#0xF0 ; a 11110000 RR a ; a 11100001 RR a Mov a,#0xF0 ; a 11110000 RR a ; a 01111000
Rotate through Carry RRC a mov a, #0A9h ; a  A9 add a, #14h ; a  BD (10111101), C0 rrc a ; a  01011110, C1 RLC a mov a, #3ch ; a  3ch(00111100) setb c ; c  1 rlc a ; a  01111001, C1 C C
Rotate and Multiplication/Division • Note that a shift left is the same as multiplying by 2, shift right is divide by 2 mov a, #3 ; A 00000011 (3) clr C ; C 0 rlc a ; A 00000110 (6) rlc a ; A 00001100 (12) rrc a ; A 00000110 (6)
Swap SWAP a mov a, #72h ; a  27h swap a ; a  27h
Bit Logic Operations • Some logic operations can be used with single bit operands ANL C, bit ORL C, bit CLR C CLR bit CPL C CPL bit SETB C SETB bit • “bit” can be any of the bit-addressable RAM locations or SFRs.
Program Flow Control • Unconditional jumps (“go to”) • Conditional jumps • Call and return
Unconditional Jumps • SJMP <rel addr> ; Short jump, relative address is 8-bit 2’s complement number, so jump can be up to 127 locations forward, or 128 locations back. • LJMP <address 16> ; Long jump • AJMP <address 11> ; Absolute jump to anywhere within 2K block of program memory • JMP @A + DPTR ; Long indexed jump
Infinite Loops Start: mov C, p3.7 mov p1.6, C sjmp Start Microcontroller application programs are almost always infinite loops!
Conditional Jump • These instructions cause a jump to occur only if a condition is true. Otherwise, program execution continues with the next instruction. loop: mov a, P1 jz loop ; if a=0, goto loop, ; else goto next instruction mov b, a • There is no zero flag (z) • Content of A checked for zero on time
Conditional jumps Mnemonic Description JZ <rel addr> Jump if a = 0 JNZ <rel addr> Jump if a != 0 JC <rel addr> Jump if C = 1 JNC <rel addr> Jump if C != 1 JB <bit>, <rel addr> Jump if bit = 1 JNB <bit>,<rel addr> Jump if bit != 1 JBC <bir>, <rel addr> Jump if bit =1, &clear bit CJNE A, direct, <rel addr> Compare A and memory, jump if not equal
More Conditional Jumps Mnemonic Description CJNE A, #data <rel addr> Compare A and data, jump if not equal CJNE Rn, #data <rel addr> Compare Rn and data, jump if not equal CJNE @Rn, #data <rel addr> Compare Rn and memory, jump if not equal DJNZ Rn, <rel addr> Decrement Rn and then jump if not zero DJNZ direct, <rel addr> Decrement memory and then jump if not zero
Iterative Loops For A = 0 to 4 do {…} clr a loop: ... ... inc a cjne a, #4, loop For A = 4 to 0 do {…} mov R0, #4 loop: ... ... djnz R0, loop
Call and Return • Call is similar to a jump, but – Call pushes PC on stack before branching acall <address ll> ; stack  PC ; PC  address 11 bit lcall <address 16> ; stack  PC ; PC  address 16 bit
Return • Return is also similar to a jump, but – Return instruction pops PC from stack to get address to jump to ret ; PC  stack
Interrupt :
Interrupt Enable Register : • EA : Global enable/disable. • --- : Undefined. • ET2 :Enable Timer 2 interrupt. • ES :Enable Serial port interrupt. • ET1 :Enable Timer 1 interrupt. • EX1 :Enable External 1 interrupt. • ET0 : Enable Timer 0 interrupt. • EX0 : Enable External 0 interrupt.
Interrupts … mov a, #2 mov b, #16 mul ab mov R0, a mov R1, b mov a, #12 mov b, #20 mul ab add a, R0 mov R0, a mov a, R1 addc a, b mov R1, a end Program Execution interrupt ISR: inc r7 mov a,r7 jnz NEXT cpl P1.6 NEXT: reti return
Interrupt Priorities • What if two interrupt sources interrupt at the same time? • The interrupt with the highest PRIORITY gets serviced first. • All interrupts have a power on default priority order. 1. External interrupt 0 (INT0)-0003h 2. Timer interrupt0 (TF0)-000Bh 3. External interrupt 1 (INT1)-0013h 4. Timer interrupt1 (TF1)-001Bh 5. Serial communication (RI+TI)-0023h • Priority can also be set to “high” or “low” by IP reg.
Interrupt Priorities (IP) Register IP.7: reserved IP.6: reserved IP.5: timer 2 interrupt priority bit(8052 only) IP.4: serial port interrupt priority bit IP.3: timer 1 interrupt priority bit IP.2: external interrupt 1 priority bit IP.1: timer 0 interrupt priority bit IP.0: external interrupt 0 priority bit --- PX0 PT0 PX1 PT1 PS PT2 ---

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Unit 4 Introduction to Microcontrollers.pptxUnit-3 IO Interfacing-1.pptximportant questions to be noted

  • 1.
    UNIT-IV: 8051 Microcontroller Architecture,I/O ports, register set, Memory organization, Addressing modes and Instruction set of 8051, Interrupts in 8051, Interrupt Priority in the 8051.
  • 2.
    Intruduction • Microprocessor =CPU on a single chip. – ALU + registers + control +… • Micro-computer = small computer – uP + I/O + memory + peripheral + … • Microcontroller (uC) – u-Computer on a single chip of silicon
  • 3.
    uP vs. uC A uP  single-chip contained only CPU  bus is available  RAM capacity, num of port is selectable  RAM is larger than ROM (usually)  A uC  single-chip contained CPU, RAM, ROM, Prepherals, I/O port  Communicate by port  internal hardware is fixed  ROM is larger than RAM (usually)
  • 4.
    8051 Basic Component •4K bytes internal ROM • 128 bytes internal RAM • Four 8-bit I/O ports (P0 - P3). • Two 16-bit timers/counters • One serial interface RAM I/O Port Timer Serial COM Port Microcontroller CPU A single chip ROM
  • 5.
    Block Diagram CPU Interrupt Control OSC Bus Control 4k ROM Timer1 Timer 2 Serial 128 bytes RAM 4 I/O Ports TXD RXD External Interrupts P0 P2 P1 P3 Addr/Data
  • 6.
    Other 8051 featurs •only 1 On chip oscillator (external crystal) • 6 interrupt sources (2 external , 3 internal, Reset) • 64K external code (program) memory(only read)PSEN • 64K external data memory(can be read and write) by RD,WR • Code memory is selectable by EA (internal or external) • We may have External memory as data and code
  • 7.
  • 8.
  • 9.
    Important Pins • PSEN’(out): Program Store Enable – Read for External Code Memory (active low) • ALE (out): Address Latch Enable – to latch address outputs at Port0 and Port2 • EA’ (in): External Access Enable – to access external program memory 0 to 4K (active low) • RXD,TXD: UART pins for serial I/O on Port 3 • Vcc （ pin 40 ） : +5V (3~5V for 89LV51) • GND （ pin 20 ） : ground • XTAL1 , XTAL2 （ pins 19,18 ） 9 • RST （ pin 9 ）： reset (active high)
  • 10.
    Important Pins (IOPorts) • One of the most useful features = four I/O ports (P0 - P3) • Port 0 ： P0 （ P0.0 ～ P0.7 ） – 8-bit R/W - General Purpose I/O – low byte address and data bus for external memory • Port 1 ： P1 （ P1.0 ～ P1.7 ） – Only 8-bit R/W - General Purpose I/O • Port 2 ： P2 （ P2.0 ～ P2.7 ） – 8-bit R/W - General Purpose I/O – high byte address for external memory • Port 3 ： P3 （ P3.0 ～ P3.7 ） – General Purpose I/O – Timers(T0,T1) – ext. int (INT0, INT1) – Serial (TXD, RXD)- RD,WR • Each port can be used as input or output (bi-direction)
  • 11.
  • 12.
    Hardware Structure ofI/O Pin D Q Clk Q Vcc Internal Pull-Up Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X B1 B2
  • 13.
    Hardware Structure ofI/O Pin • Each pin of I/O ports – Internally connected to CPU bus – A D latch store the value of this pin • Write to latch ＝ 1 ： write data into the D latch – 2 Tri-state buffer ： • B1: controlled by “Read pin” – Read pin ＝ 1 ： really read the data present at the pin • B2: controlled by “Read latch” – Read latch ＝ 1 ： read value from internal latch – A transistor M1 gate • Gate=0: open • Gate=1: close
  • 14.
    Writing “1” toOutput Pin P1.X D Q Clk Q Vcc Internal Pull-Up Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X 2. output pin is Vcc 1. write a 1 to the pin 1 0 output 1 B1 B2
  • 15.
    Writing “0” toOutput Pin P1.X D Q Clk Q Vcc Internal Pull-Up Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X 2. output pin is ground 1. write a 0 to the pin 0 1 output 0 B1 B2
  • 16.
  • 18.
    Types of Memory External DATA Memory ( upto 64KB ) RAM External CODE Memory ( up to 64KB ) ROM 8051 Chip 0000h FFFFh FFFFh Internal RAM SFRs Internal code Memory ( EEPROM ) 0000h
  • 19.
    Types of Memory •External Code Memory (64k) • External RAM Data Memory (64k) • Internal Code Memory – 4k,8k,12k,20k – ROM, EPROM, EEPROM • Internal RAM – First 128 bytes: 00h to 1Fh Register Banks 20h to 2Fh Bit Addressable RAM 30 to 7Fh General Purpose RAM – Next 128 bytes: 80h to FFh Special Function Registers
  • 20.
    External Memory • /EA（ pin 31 ）： external access – /EA=‘0’ indicates that code is stored externally. – /PSEN ＆ ALE are used for external ROM. – For 8051 internal code, /EA pin is connected to Vcc. – “/” means active low. • /PSEN （ pin 29 ）： program store enable – Output- connected to OE of ROM. – Read signal – fetch from ROM
  • 21.
    External Memory • ALE（ pin 30 ） : address latch enable – It is an output pin and is active high – 8051 port 0 provides both address and data – The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.
  • 23.
  • 24.
    General Purpose Register 07 06 05 04 03 02 01 00 R7 R6 R5 R4 R3 R2 R1 R0 0F 08 17 10 1F 18 Bank3 Bank 2 Bank 1 Bank 0 4 Register Banks Each bank has R0-R7 Selectable by PSW.2,3
  • 25.
    Bit Addressable Memory 20h– 2Fh (16 locations  8-bits = 128 bits) 7F 78 1A 10 0F 08 07 06 05 04 03 02 01 00 27 26 25 24 23 22 21 20 2F 2E 2D 2C 2B 2A 29 28 Bit addressing: mov C, 1Ah or mov C, 23h.2
  • 26.
    Special Function Registers DATAregisters CONTROL registers Timers Serial ports Interrupt system Analog to Digital converter Digital to Analog converter Etc. Addresses 80h – FFh Direct Addressing used to access SFRs
  • 27.
    Summary of on-chipdata memory (RAM) MOV C, 67H ≡ MOV C, 2CH.7
  • 28.
  • 29.
    8051 CPU Registers A(Accumulator) B PSW (Program Status Word) SP (Stack Pointer) PC (Program Counter) DPTR (Data Pointer) Used in assembler instructions
  • 30.
    Registers A B R0 R1 R3 R4 R2 R5 R7 R6 DPH DPL PC DPTR PC Some 805116-bit Register Some 8-bit Registers of the 8051
  • 31.
    Addressing Modes Immediate Mode– specify data by its value mov A, #0 ;put 0 in the accumulator ;A = 00000000 mov R4, #11h ;put 11hex in the R4 register ;R4 = 00010001 mov B, #11 ;put 11 decimal in b register ;B = 00001011 mov DPTR,#7521h ;put 7521 hex in DPTR ;DPTR = 0111010100100001
  • 32.
    Addressing Modes Register Addressing– either source or destination is one of CPU register MOV R0,A MOV A,R7 ADD A,R4 ADD A,R7 MOV DPTR,#25F5H MOV R5,DPL MOV R,DPH Note that MOV R4,R7 is incorrect
  • 33.
    Addressing Modes Direct Mode– specify data by its 8-bit address Usually for 30h-7Fh of RAM Mov a, 70h ; copy contents of RAM at 70h to a Mov R0,40h ; copy contents of RAM at 40h to R0 Mov 56h,a ; put contents of a at 56h to a Mov 0D0h,a ; put contents of a into PSW
  • 34.
    Addressing Modes Register Indirect– the address of the source or destination is specified in registers Uses registers R0 or R1 for 8-bit address: mov psw, #0 ; use register bank 0 mov r0, #0x3C mov @r0, #3 ; memory at 3C gets #3 ; M[3C]  3 Uses DPTR register for 16-bit addresses: mov dptr, #0x9000 ; dptr  9000h movx a, @dptr ; a  M[9000] Note that 9000 is an address in external memory
  • 35.
    Addressing Modes Register IndexedMode – source or destination address is the sum of the base address and the accumulator(Index) • Base address can be DPTR or PC mov dptr, #4000h mov a, #5 movc a, @a + dptr ;a  M[4005]
  • 36.
  • 37.
    Overview • Data transferinstructions • Addressing modes • Data processing (arithmetic and logic) • Program flow instructions
  • 38.
    Data Transfer Instructions •MOV dest, source dest  source • Stack instructions PUSH byte ;increment stack pointer, ;move byte on stack POP byte ;move from stack to byte, ;decrement stack pointer • Exchange instructions XCH a, byte ;exchange accumulator and byte XCHD a, byte ;exchange low nibbles of ;accumulator and byte
  • 39.
    Exchange Instructions two waydata transfer XCH a, 30h ; a  M[30] XCH a, R0 ; a  R0 XCH a, @R0 ; a  M[R0] XCHD a, R0 ; exchange “digit” R0[7..4] R0[3..0] a[7..4] a[3..0] Only 4 bits exchanged
  • 40.
    Data Processing Instructions ArithmeticInstructions Logic Instructions
  • 41.
    Arithmetic Instructions • Add •Subtract • Increment • Decrement • Multiply • Divide • Decimal adjust
  • 42.
    Arithmetic Instructions Mnemonic Description ADDA, byte add A to byte, put result in A ADDC A, byte add with carry SUBB A, byte subtract with borrow INC A increment A INC byte increment byte in memory INC DPTR increment data pointer DEC A decrement accumulator DEC byte decrement byte MUL AB multiply accumulator by b register DIV AB divide accumulator by b register DA A decimal adjust the accumulator
  • 43.
    ADD Instructions add a,byte ; a  a + byte addc a, byte ; a  a + byte + C These instructions affect 3 bits in PSW: C = 1 if result of add is greater than FF AC = 1 if there is a carry out of bit 3 OV = 1 if there is a carry out of bit 7, but not from bit 6, or visa versa.
  • 44.
  • 45.
    ADD Examples mov a,#3Fh add a, #D3h • What is the value of the C, AC, OV flags after the second instruction is executed? 0011 1111 1101 0011 10001 0010 C = 1 AC = 1 OV = 0
  • 46.
    Signed Addition andOverflow 0111 1111 (positive 127) 0111 0011 (positive 115) 1111 0010 (overflow cannot represent 242 in 8 bits 2’s complement) 2’s complement: 0000 0000 00 0 … 0111 1111 7F 127 1000 0000 80 -128 … 1111 1111 FF -1 1000 1111 (negative 113) 1101 0011 (negative 45) 0110 0010 (overflow) 0011 1111 (positive) 1101 0011 (negative) 0001 0010 (never overflows)
  • 47.
    Addition Example ; ComputesZ = X + Y ; Adds values at locations 78h and 79h and puts them in 7Ah ;------------------------------------------------------------------ X equ 78h Y equ 79h Z equ 7Ah ;----------------------------------------------------------------- org 00h ljmp Main ;----------------------------------------------------------------- org 100h Main: mov a, X add a, Y mov Z, a end
  • 48.
    Subtract SUBB A, bytesubtract with borrow Example: SUBB A, #0x4F ;A  A – 4F – C Notice that There is no subtraction WITHOUT borrow. Therefore, if a subtraction without borrow is desired, it is necessary to clear the C flag. Example: Clr c SUBB A, #0x4F ;A  A – 4F
  • 49.
    Increment and Decrement •The increment and decrement instructions do NOT affect the C flag. • Notice we can only INCREMENT the data pointer, not decrement. INC A increment A INC byte increment byte in memory INC DPTR increment data pointer DEC A decrement accumulator DEC byte decrement byte
  • 50.
    Example: Increment 16-bitWord • Assume 16-bit word in R3:R2 mov a, r2 add a, #1 ; use add rather than increment to affect C mov r2, a mov a, r3 addc a, #0 ; add C to most significant byte mov r3, a
  • 51.
    Multiply When multiplying two8-bit numbers, the size of the maximum product is 16-bits FF x FF = FE01 (255 x 255 = 65025) MUL AB ; BA  A * B Note : B gets the High byte A gets the Low byte
  • 52.
    Division • Integer Division DIVAB ; divide A by B A  Quotient(A/B) B  Remainder(A/B) OV - used to indicate a divide by zero condition. C – set to zero
  • 53.
    Decimal Adjust DA a; decimal adjust a Used to facilitate BCD addition. Adds “6” to either high or low nibble after an addition to create a valid BCD number. Example: mov a, #23h mov b, #29h add a, b ; a  23h + 29h = 4Ch (wanted 52) DA a ; a  a + 6 = 52
  • 54.
    Logic Instructions  Bitwiselogic operations  (AND, OR, XOR, NOT)  Clear  Rotate  Swap Logic instructions do NOT affect the flags in PSW
  • 55.
    Bitwise Logic ANL AND ORL  OR XRL  XOR CPL  Complement Examples: 00001111 10101100 ANL 00001111 10101100 ORL 00001111 10101100 XRL 10101100 CPL 00001100 10101111 10100011 01010011
  • 56.
    Address Modes withLogic a, byte direct, reg. indirect, reg, immediate byte, a direct byte, #constant a ex: cpl a ANL – AND ORL – OR XRL – eXclusive oR CPL – Complement
  • 57.
    Uses of LogicInstructions • Force individual bits low, without affecting other bits. anl PSW, #0xE7 ;PSW AND 11100111 • Force individual bits high. orl PSW, #0x18 ;PSW OR 00011000 • Complement individual bits xrl P1, #0x40 ;P1 XRL 01000000
  • 58.
    Other Logic Instructions CLR- clear RL – rotate left RLC – rotate left through Carry RR – rotate right RRC – rotate right through Carry SWAP – swap accumulator nibbles
  • 59.
    CLR ( Setall bits to 0) CLR A CLR byte (direct mode) CLR Ri (register mode) CLR @Ri (register indirect mode)
  • 60.
    Rotate • Rotate instructionsoperate only on a RL a Mov a,#0xF0 ; a 11110000 RR a ; a 11100001 RR a Mov a,#0xF0 ; a 11110000 RR a ; a 01111000
  • 61.
    Rotate through Carry RRCa mov a, #0A9h ; a  A9 add a, #14h ; a  BD (10111101), C0 rrc a ; a  01011110, C1 RLC a mov a, #3ch ; a  3ch(00111100) setb c ; c  1 rlc a ; a  01111001, C1 C C
  • 62.
    Rotate and Multiplication/Division •Note that a shift left is the same as multiplying by 2, shift right is divide by 2 mov a, #3 ; A 00000011 (3) clr C ; C 0 rlc a ; A 00000110 (6) rlc a ; A 00001100 (12) rrc a ; A 00000110 (6)
  • 63.
    Swap SWAP a mov a,#72h ; a  27h swap a ; a  27h
  • 64.
    Bit Logic Operations •Some logic operations can be used with single bit operands ANL C, bit ORL C, bit CLR C CLR bit CPL C CPL bit SETB C SETB bit • “bit” can be any of the bit-addressable RAM locations or SFRs.
  • 65.
    Program Flow Control •Unconditional jumps (“go to”) • Conditional jumps • Call and return
  • 66.
    Unconditional Jumps • SJMP<rel addr> ; Short jump, relative address is 8-bit 2’s complement number, so jump can be up to 127 locations forward, or 128 locations back. • LJMP <address 16> ; Long jump • AJMP <address 11> ; Absolute jump to anywhere within 2K block of program memory • JMP @A + DPTR ; Long indexed jump
  • 67.
    Infinite Loops Start: movC, p3.7 mov p1.6, C sjmp Start Microcontroller application programs are almost always infinite loops!
  • 68.
    Conditional Jump • Theseinstructions cause a jump to occur only if a condition is true. Otherwise, program execution continues with the next instruction. loop: mov a, P1 jz loop ; if a=0, goto loop, ; else goto next instruction mov b, a • There is no zero flag (z) • Content of A checked for zero on time
  • 69.
    Conditional jumps Mnemonic Description JZ<rel addr> Jump if a = 0 JNZ <rel addr> Jump if a != 0 JC <rel addr> Jump if C = 1 JNC <rel addr> Jump if C != 1 JB <bit>, <rel addr> Jump if bit = 1 JNB <bit>,<rel addr> Jump if bit != 1 JBC <bir>, <rel addr> Jump if bit =1, &clear bit CJNE A, direct, <rel addr> Compare A and memory, jump if not equal
  • 70.
    More Conditional Jumps MnemonicDescription CJNE A, #data <rel addr> Compare A and data, jump if not equal CJNE Rn, #data <rel addr> Compare Rn and data, jump if not equal CJNE @Rn, #data <rel addr> Compare Rn and memory, jump if not equal DJNZ Rn, <rel addr> Decrement Rn and then jump if not zero DJNZ direct, <rel addr> Decrement memory and then jump if not zero
  • 71.
    Iterative Loops For A= 0 to 4 do {…} clr a loop: ... ... inc a cjne a, #4, loop For A = 4 to 0 do {…} mov R0, #4 loop: ... ... djnz R0, loop
  • 72.
    Call and Return •Call is similar to a jump, but – Call pushes PC on stack before branching acall <address ll> ; stack  PC ; PC  address 11 bit lcall <address 16> ; stack  PC ; PC  address 16 bit
  • 73.
    Return • Return isalso similar to a jump, but – Return instruction pops PC from stack to get address to jump to ret ; PC  stack
  • 74.
  • 75.
    Interrupt Enable Register: • EA : Global enable/disable. • --- : Undefined. • ET2 :Enable Timer 2 interrupt. • ES :Enable Serial port interrupt. • ET1 :Enable Timer 1 interrupt. • EX1 :Enable External 1 interrupt. • ET0 : Enable Timer 0 interrupt. • EX0 : Enable External 0 interrupt.
  • 76.
    Interrupts … mov a, #2 movb, #16 mul ab mov R0, a mov R1, b mov a, #12 mov b, #20 mul ab add a, R0 mov R0, a mov a, R1 addc a, b mov R1, a end Program Execution interrupt ISR: inc r7 mov a,r7 jnz NEXT cpl P1.6 NEXT: reti return
  • 77.
    Interrupt Priorities • Whatif two interrupt sources interrupt at the same time? • The interrupt with the highest PRIORITY gets serviced first. • All interrupts have a power on default priority order. 1. External interrupt 0 (INT0)-0003h 2. Timer interrupt0 (TF0)-000Bh 3. External interrupt 1 (INT1)-0013h 4. Timer interrupt1 (TF1)-001Bh 5. Serial communication (RI+TI)-0023h • Priority can also be set to “high” or “low” by IP reg.
  • 78.
    Interrupt Priorities (IP)Register IP.7: reserved IP.6: reserved IP.5: timer 2 interrupt priority bit(8052 only) IP.4: serial port interrupt priority bit IP.3: timer 1 interrupt priority bit IP.2: external interrupt 1 priority bit IP.1: timer 0 interrupt priority bit IP.0: external interrupt 0 priority bit --- PX0 PT0 PX1 PT1 PS PT2 ---