Unit 5Memory management.pptx

Memory Management
 Background
 Swapping
 Contiguous Allocation
 Paging
 Segmentation
 Segmentation with Paging

Background
 Program must be brought into memory and placed within a
process for it to be run
 Input queue – collection of processes on the disk that are
waiting to be brought into memory to run the program
 User programs go through several steps before being run

Binding of Instructions and Data to Memory
 Compile time
 Load time
 Execution time
Address binding of instructions and data to memory addresses can
happen at three different stages

Logical vs. Physical Address Space
 The concept of a logical address space that is bound to a
separate physical address space is central to proper memory
management
 Logical address – generated by the CPU; also referred to as
virtual address
 Physical address – address seen by the memory unit
 Logical and physical addresses are the same in compile-time and
load-time address-binding schemes; logical (virtual) and physical
addresses differ in execution-time address-binding scheme

Memory-Management Unit (MMU)
 Hardware device that maps virtual to physical address
 In MMU scheme, the value in the relocation register is
added to every address generated by a user process at
the time it is sent to memory
 The user program deals with logical addresses; it never
sees the real physical addresses

Dynamic relocation using a relocation register

Dynamic Loading
 Routine is not loaded until it is called
 Better memory-space utilization; unused routine is never
loaded
 Useful when large amounts of code are needed to handle
infrequently occurring cases
 No special support from the operating system is required
implemented through program design

Swapping
 A process can be swapped temporarily out of memory to a backing
store, and then brought back into memory for continued execution
 Backing store – fast disk large enough to accommodate copies of
all memory images for all users; must provide direct access to these
memory images
 Roll out, roll in – swapping variant used for priority-based
scheduling algorithms; lower-priority process is swapped out so
higher-priority process can be loaded and executed
 Major part of swap time is transfer time; total transfer time is directly
proportional to the amount of memory swapped
 Modified versions of swapping are found on many systems (i.e.,
UNIX, Linux, and Windows)

Contiguous Allocation
 Main memory usually divided into two partitions:
 Resident operating system, usually held in low memory with
interrupt vector
 User processes then held in high memory

A base and a limit register define a logical address space

HW address protection with base and limit registers

Contiguous Allocation (Cont.)
 Multiple-partition allocation
 Hole – block of available memory; holes of various size are
scattered throughout memory
 When a process arrives, it is allocated memory from a hole
large enough to accommodate it
 Operating system maintains information about:
a) allocated partitions b) free partitions (hole)
OS
process 5
process 8
process 2
OS
process 5
process 2
OS
process 5
process 2
OS
process 5
process 9
process 2
process 9
process 10

Dynamic Storage-Allocation Problem
 First-fit: Allocate the first hole that is big enough
 Best-fit: Allocate the smallest hole that is big enough; must search
entire list, unless ordered by size. Produces the smallest leftover
hole.
 Worst-fit: Allocate the largest hole; must also search entire list.
Produces the largest leftover hole.
How to satisfy a request of size n from a list of free holes
First-fit and best-fit better than worst-fit in terms of
speed and storage utilization

Fragmentation
 External Fragmentation – total memory space exists to
satisfy a request, but it is not contiguous
 Internal Fragmentation – allocated memory may be
slightly larger than requested memory; this size difference is
memory internal to a partition, but not being used
 Reduce external fragmentation by compaction
 Shuffle memory contents to place all free memory
together in one large block

Paging
 Logical address space of a process can be noncontiguous; process is
allocated physical memory whenever the latter is available
 Divide physical memory into fixed-sized blocks called frames (size is
power of 2, between 512 bytes and 8192 bytes)
 Divide logical memory into blocks of same size called pages.
 Keep track of all free frames
 To run a program of size n pages, need to find n free frames and load
program
 Set up a page table to translate logical to physical addresses
 Internal fragmentation

Address Translation Scheme
 Address generated by CPU is divided into:
 Page number (p) – used as an index into a page table
which contains base address of each page in physical
memory
 Page offset (d) – combined with base address to define
the physical memory address that is sent to the memory
unit

Address Translation Architecture

Free Frames
Before allocation After allocation

Implementation of Page Table
 Page table is kept in main memory
 Page-table base register (PTBR) points to the page
table
 Page-table length register indicates size of the page
table
 In this scheme every data/instruction access requires
two memory accesses. One for the page table and
one for the data/instruction.
 The two memory access problem can be solved by the
use of a special fast-lookup hardware cache called
associative memory or translation look-aside
buffers (TLBs)

Memory Protection
 Memory protection implemented by associating
protection bit with each frame
 Valid-invalid bit attached to each entry in the page
table:
 “valid” indicates that the associated page is in the
process’ logical address space, and is thus a legal
page
 “invalid” indicates that the page is not in the process’
logical address space

Valid (v) or Invalid (i) Bit In A Page Table

Two-Level Paging Example
 A logical address (on 32-bit machine with 4K page size) is divided into:
 a page number consisting of 20 bits
 a page offset consisting of 12 bits
 Since the page table is paged, the page number is further divided into:
 a 10-bit page number
 a 10-bit page offset
 Thus, a logical address is as follows:
 where pi is an index into the outer page table, and p2 is the displacement within the
page of the outer page table
page number page offset
pi p2 d
10 10 12

Address-Translation Scheme
 Address-translation scheme for a two-level 32-bit paging
architecture

Inverted Page Table
 One entry for each real page of memory
 Entry consists of the virtual address of the page stored in
that real memory location, with information about the
process that owns that page
 Decreases memory needed to store each page table, but
increases time needed to search the table when a page
reference occurs
 Use hash table to limit the search to one — or at most a
few — page-table entries

Inverted Page Table Architecture

Segmentation
 Memory-management scheme that supports user view of memory
 A program is a collection of segments. A segment is a logical unit
such as:
main program,
procedure,
function,
method,
object,
local variables, global variables,
common block,
stack,
symbol table, arrays

Logical View of Segmentation
1
3
2
4
1
4
2
3
user space physical memory space

Unit 5Memory management.pptx

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Unit 5Memory management.pptx