Unit 5_Realizing Applications in FPGA.pdf
- 1. PROGRAMMING IN HDL(SECA1605) MENTOR Dr.T.RAVI Department of ECE Sathyabama Institute of Science and Technology
- 2. Course Outcome After the completion of course student will be able to CO1 Understand the requirements of VHDL design flow CO2 Interpret the Verilog language elements and its relevance to digital design CO3 Apply the Modelling Styles for Simulation, Synthesis and Test Bench Creation. CO4 Analyse the Performance Study of Combinational and Sequential logic design using Verilog CO5 Evaluate State Machine and Memory designs by Verilog CO6 Create and realize the system in FPGA using Verilog
- 3. UNIT 5 REALIZING APPLICATIONS IN FPGA FPGA Design Flow - Architecture of Xilinx Artix7 FPGA - Configurable Logic Blocks (CLB)- Slice Description- LUT - Storage element - Programmable Interconnect - Internal Hard macros - Realizing applications in FPGA - combinational functions - N-bit functions, Encoder, Decoders - Sequential functions - N-bit register, shift registers, up/down counters- N-bit processor. Case Study: study of protocols I2C, SPI and UART.
- 7. FPGA Design Translation • CAD to translate circuit from text description to physi cal implementation • Most current FPGA designers use register-transfer l evel specification RTL . . C = A+B . Circuit A B + C Array
- 8. Register Transfer-Level Design • A register-transfer machine has combinational logic connecting registers: D Q Combinational Logic D Q D Q Combinational Logic Combinational Logic
- 9. Lect-14.9 FPGA Circuit Compilation • Technology Mapping • Placement • Routing LUT LUT Assign a logical LUT to a physical location Select wire segments and switches for interconnection
- 10. Lect-14.10 FPGA Design Flow (Xilinx) Design Entry Synthesis Implementation Device Programming Functional Simulation Timing Simulation HDL files, schematics EDIF/XNF netlist NGD Xilinx primitives file FPGA bitstream
- 11. Lect-14.11 Design Flow with Test Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end RC5_core; Specification VHDL description Functional simulation Post-synthesis simulation Synthesized Circuit
- 12. Lect-14.12 Design Flow with Test (cont.) Implementation Configuration Timing simulation On chip testing Post-synthesis simulation Synthesized Circuit
- 13. Lect-14.13 Implementation Implementation UCF NGD EDIF NCF Native Generic Database file Constraint Editor User Constraint File Native Constraint File Electronic Design Interchange Format Circuit netlist Timing Constraints Synthesis
- 14. Lect-14.14 Circuit Netlist and Mapping LUT2 LUT3 LUT4 LUT5 FF1 FF2 LUT1 LUT0
- 15. Lect-14.15 Placing and Routing Programmable Connections FPGA
- 16. Lect-14.16 Configuration • Once a design is implemented, you must create a file that the FPGA can understand • This file is called a bit stream: a BIT file (.bit extension) • The BIT file can be downloaded directly to the FPGA, or can be converted into a PROM file which stores the programming information
- 17. Consists of… • Real 6-input look-up table (LUT) technology • Dual LUT5 (5-input LUT) option • Distributed Memory and Shift Register Logic capability • Dedicated high-speed carry logic for arithmetic functions • Wide multiplexers for efficient utilization 7 series configurable logic block (CLB) ➢ CLBs are the main logic resources for implementing sequential as well as combinatorial circuits ➢ Each CLB element is connected to a switch matrix for access to the general routing matrix
- 18. Arrangement of Slices within the CLB
- 19. 7 Series FPGA
- 20. Row and Column Relationship between CLBs and Slices
- 22. SLICEM
- 23. SLICEL