Verilog code all
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This document contains Verilog code for several basic digital logic components: a 4:1 multiplexer, JK flip-flop, 4-to-2 encoder, 2-to-4 decoder, 1:4 demultiplexer, asynchronous counter that counts from 0-3 repeatedly, and a skipping counter that counts 0-1-3-0 repeatedly. Each component is defined in a separate module with inputs, outputs, and logic assignments to implement the desired function.
![1:4 demux
module jugad5(y0,y1,y2,y3,s1,s0,i);
output y0,y1,y2,y3;
input s1,s0,i;
assign y0=!s1&&!s0&&i;
assign y1=!s1&&s0&&i;
assign y2=s1&&!s0&&i;
assign y3=s1&&s0&&i;
endmodule
Asynchronous countor
module jugad6( q_out, qbar_out, j,k, clk, reset);
input [1:0] j; input [1:0] k; input clk; input reset;
output [1:0] q_out;
output [1:0] qbar_out;
wire [1:0] q_out;
wire [1:0] qbar_out;
wire clk;
assign qbar_out[0] = ~q_out[0];
assign j[0] = 1;
assign k[0] = 1;
assign j[1] = 1;](https://image.slidesharecdn.com/verilogcode-151120104818-lva1-app6891/85/Verilog-code-all-3-320.jpg)
![assign k[1] = 1;
jkff M1(q_out[0], qbar_out[0], j[0], k[0], clk, reset);
jkff M2(q_out[1], qbar_out[1], j[1], k[1], qbar_out[0]);
endmodule
module jkff(output q_out, output qbar_out,
input j, input k, input clk, input reset);
reg q;
assign q_out = q;
assign qbar_out = ~q;
initial begin
q = 1'b0;
end
always @(posedge clk)
begin
case({j,k})
{1'b0, 1'b0}: begin
q = q;
end
{1'b0, 1'b1}: begin
q = 1'b0;
end
{1'b1, 1'b0}: begin](https://image.slidesharecdn.com/verilogcode-151120104818-lva1-app6891/85/Verilog-code-all-4-320.jpg)
![q = 1'b1;
end
{1'b1, 1'b1}: begin
q = ~q;
end
endcase
end
always @(posedge reset)
begin
q = 1'b0;
end
endmodule
skipping counter(0->1->3->0)
module jugad7( q_out, qbar_out, j,k, clk, reset);
input [1:0] j; input [1:0] k; input clk; input reset;
output [1:0] q_out;
output [1:0] qbar_out;
wire [1:0] q_out;
wire [1:0] qbar_out;
wire clk;
assign qbar_out[0] = ~q_out[0];
assign j[0]=!q_out[1];
assign j[1]=q_out[0];
assign k[0] =q_out[1];](https://image.slidesharecdn.com/verilogcode-151120104818-lva1-app6891/85/Verilog-code-all-5-320.jpg)
![assign k[1] =1;
jkff M1(q_out[0], qbar_out[0], j[0], k[0], clk, reset);
jkff M2(q_out[1], qbar_out[1], j[1], k[1], clk,reset);
endmodule
module jkff(output q_out, output qbar_out,
input j, input k, input clk, input reset);
reg q;
assign q_out = q;
assign qbar_out = ~q;
initial begin
q = 1'b0;
end
always @(posedge clk)
begin
case({j,k})
{1'b0, 1'b0}: begin
q = q;
end
{1'b0, 1'b1}: begin
q = 1'b0;
end](https://image.slidesharecdn.com/verilogcode-151120104818-lva1-app6891/85/Verilog-code-all-6-320.jpg)
Verilog code all
- 1. 4:1mux module 4:1mux(s0,s1,i0,i1,i2,i3,y); outputy; inputs0,s1,i0,i1,i2,i3; assigny=((!s1)&&(!s0)&&(i0))||((!s1)&&(s0)&&(i1))||((s1)&&(!s0)&&(i2))||((s1)&&(s0)&&(i3)); endmodule jk flipflop module jk(q,q1,j,k,c); outputq,q1; inputj,k,c; reg q,q1; initial beginq=1'b0;q1=1'b1; end always@ (posedge c) begin case({j,k}) {1'b0,1'b0}:beginq=q; q1=q1; end {1'b0,1'b1}: beginq=1'b0; q1=1'b1; end {1'b1,1'b0}:beginq=1'b1; q1=1'b0; end {1'b1,1'b1}: beginq=~q; q1=~q1; end endcase end endmodule
- 2. 4*2 encoder module jugad3(d0,d1,d2,d3,b1,b0); input d0,d1,d2,d3; output b1,b0; assign b0=d1||d3; assign b1=d2||d3; endmodule 2*4 decoder module jugad4(d0,d1,d2,d3,b1,b0); output d0,d1,d2,d3; input b1,b0; assign d0=(!b1)&&(!b0); assign d1=(!b1)&&(b0); assign d2=(b1)&&(!b0); assign d3=(b1)&&(b0); endmodule
- 3. 1:4 demux module jugad5(y0,y1,y2,y3,s1,s0,i); output y0,y1,y2,y3; input s1,s0,i; assign y0=!s1&&!s0&&i; assign y1=!s1&&s0&&i; assign y2=s1&&!s0&&i; assign y3=s1&&s0&&i; endmodule Asynchronous countor module jugad6( q_out, qbar_out, j,k, clk, reset); input [1:0] j; input [1:0] k; input clk; input reset; output [1:0] q_out; output [1:0] qbar_out; wire [1:0] q_out; wire [1:0] qbar_out; wire clk; assign qbar_out[0] = ~q_out[0]; assign j[0] = 1; assign k[0] = 1; assign j[1] = 1;
- 4. assign k[1] = 1; jkff M1(q_out[0], qbar_out[0], j[0], k[0], clk, reset); jkff M2(q_out[1], qbar_out[1], j[1], k[1], qbar_out[0]); endmodule module jkff(output q_out, output qbar_out, input j, input k, input clk, input reset); reg q; assign q_out = q; assign qbar_out = ~q; initial begin q = 1'b0; end always @(posedge clk) begin case({j,k}) {1'b0, 1'b0}: begin q = q; end {1'b0, 1'b1}: begin q = 1'b0; end {1'b1, 1'b0}: begin
- 5. q = 1'b1; end {1'b1, 1'b1}: begin q = ~q; end endcase end always @(posedge reset) begin q = 1'b0; end endmodule skipping counter(0->1->3->0) module jugad7( q_out, qbar_out, j,k, clk, reset); input [1:0] j; input [1:0] k; input clk; input reset; output [1:0] q_out; output [1:0] qbar_out; wire [1:0] q_out; wire [1:0] qbar_out; wire clk; assign qbar_out[0] = ~q_out[0]; assign j[0]=!q_out[1]; assign j[1]=q_out[0]; assign k[0] =q_out[1];
- 6. assign k[1] =1; jkff M1(q_out[0], qbar_out[0], j[0], k[0], clk, reset); jkff M2(q_out[1], qbar_out[1], j[1], k[1], clk,reset); endmodule module jkff(output q_out, output qbar_out, input j, input k, input clk, input reset); reg q; assign q_out = q; assign qbar_out = ~q; initial begin q = 1'b0; end always @(posedge clk) begin case({j,k}) {1'b0, 1'b0}: begin q = q; end {1'b0, 1'b1}: begin q = 1'b0; end
- 7. {1'b1, 1'b0}: begin q = 1'b1; end {1'b1, 1'b1}: begin q = ~q; end endcase end always @(posedge reset) begin q = 1'b0; end endmodule