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2025_7_25_吉祥寺_設計ナイト_ADR運用におけるデータ利活用の考え方.pptxssuserfcafd1
たぶんできる！Verilog hdl
- 2. Syntax
1 module adder(a, b, y);
2 input [7:0] a, b;
3 output [7:0] y;
4
5 assign y = a + b;
6
7 endmodule adder
a
b
8
8
8
y
2
- 4. 16bit Counter
7 reg [15:0] creg; //16bit register
8 always @(posedge clk) begin
9 if(rst == 1’b0)
10 creg <= 0;
11 else
12 creg <= creg + 1;
13 end
14 assign out = creg;
15 endmodule
4
![Syntax
1 module adder(a, b, y);
2 input [7:0] a, b;
3 output [7:0] y;
4
5 assign y = a + b;
6
7 endmodule adder
a
b
8
8
8
y
2](https://image.slidesharecdn.com/verilog-hdl-141220020647-conversion-gate01/85/Verilog-hdl-2-320.jpg)
![16bit Counter
7 reg [15:0] creg; //16bit register
8 always @(posedge clk) begin
9 if(rst == 1’b0)
10 creg <= 0;
11 else
12 creg <= creg + 1;
13 end
14 assign out = creg;
15 endmodule
4](https://image.slidesharecdn.com/verilog-hdl-141220020647-conversion-gate01/85/Verilog-hdl-4-320.jpg)
