VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions

The power of partnership. The triumph of technology. VHDL Packages Coding Styles for Arithmetic Operations VHDL-200x Additions

Agenda Introduction VHDL Libraries & Packages The Two Camps (IEEE vs Synopsys) Coding Arithmetic Operations in VHDL VHDL-200x Additions Cores, cores, cores...

Introduction VHDL is a strongly typed language Allows overloading of operators/functions/procedures. Two different ways of coding arithmetic operations because of two different camps (IEEE, Synopsys) IEEE is the recommended way, it is being revised by Accllera as new VHDL-200x

VHDL Libraries and Packages STD library packages standard, textio IEEE library packages +(new) std_logic_1164, numeric_bit, (numeric_bit_unsigned), numeric_std, (numeric_std_unsigned) math_real, math_complex, (fixed_generic_pkg), (fixed_pkg, float_generic_pkg), (float_pkg), (...) Synopsys library packages (compiled into IEEE library!) std_logic_arith, std_logic_unsigned, std_logic_signed, std_logic_misc, std_logic_textio

STD.Standard VHDL Native Data Types boolean false, true bit '0', '1' character 256 ASCII string array of character integer -2 32-1 ... +(2 32-1 -1) natural 0 ... +(2 32-1 -1) positive 1 ... +(2 32-1 -1) real -1.0E38 ... +1.0E38 time 1 fs ... 1 hr

STD.Textio Constants input (STDIN), output (STDOUT) Data Types LINE, TEXT, SIDE Procedures Read/Write for standard types ReadLine/WriteLine

IEEE.std_logic_1164 Data Types std_ulogic ('U','X','0','1','Z','W','L','H','-') std_logic resolved of std_ulogic std_ulogic_vector array of std_ulogic std_logic_vector array of std_logic Operators Boolean (and/or/nand/nor/xor/xnor/not) Functions Conversion From/To std_(u)logic(_vector) To/From bit(_vector), to_x01, is_x rising_edge/falling_edge for std_(u)logic

IEEE.numeric_bit Data Types unsigned, signed --> array of bit Operators Arithmetic: +, -, *, /, rem, mod Relational: <, <=, =, /=, =>, > Shift/Rotate: sll, srl, rol, ror Bitwise: and, nand, or, nor, xor, xnor, not Functions abs, shift_left, shift_right, rotate_left, rotate_right resize, to_integer, to_signed, to_unsigned rising_edge, falling_edge for bit (will move to STD.standard)

IEEE.numeric_std Data Types unsigned, signed --> array of std_logic Operators Arithmetic: +, -, *, /, rem, mod Relational: <, <=, =, /=, =>, > Shift/Rotate: sll, srl, rol, ror Bitwise: and, nand, or, nor, xor, xnor, not Functions abs, shift_left, shift_right, rotate_left, rotate_right resize, to_integer, to_signed, to_unsigned std_match, to_01

IEEE.math_real (not synthesizable*) Constants MATH_E, MATH_PI, ... Operators for real mod, **, Functions accepting real returning real sign, ceil, floor, round, trunc, realmax, realmin, sqrt, cbrt, exp, log, log2*, log10 sin, cos, tan, arcsin, arccos, arctan sinh, cosh, tanh, arcsinh, arccosh, arctanh Procedures uniform: Pseudo-random number (0.0, 1.0)

IEEE.math_complex (not synthesizable) Data Types complex, complex_polar positive_real, principal_value (-  .. +) Operators +, -, *, /, =, /= Functions complex_to_polar, polar_to_complex abs, arg, conj, sqrt, exp, log, log2, log10 sin, cos, tan, arcsin, arccos, arctan sinh, cosh, tanh, arcsinh, arccosh, arctanh

IEEE(synopsys).std_logic_arith Data Types signed, unsigned --> array of std_logic small_int --> 0, 1 Operators Arithmetic: +, -, * Relational: <, <=, =, /=, =>, > Shift: shr, shl Functions conv_integer, conv_signed, conv_unsigned, conv_std_logic_vector ext, sxt

IEEE(synopsys).std_logic_signed Operators +, -, * <, <=, /=, =, =>, > Functions abs shl, shr conv_integer

IEEE(synopsys).std_logic_unsigned Operators +, -, * <, <=, /=, =, =>, > Functions shl, shr conv_integer

IEEE(synopsys).std_logic_textio Procedures Read/Write ORead/OWrite, HRead/HWrite for std_(u)logic(_vector) Contents will be moved to std_logic_1164 for VHDL-200x

The two camps (IEEE vs Synopsys) IEEE version library IEEE; use IEEE.std_logic_1164.all; use IEEE. numeric_bit.all; or numeric_std.all; Synopsys version library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_signed.all;

The two camps (cont.) Never mix the two libraries Either use numeric_std or std_logic_arith but not both numeric_std and std_logic_unsigned could be used together until VHDL-200x is complete. There will be new packages numeric_bit_unsigned and numeric_std_unsigned. For standard compatibility and for compliance with the future VHDL-200x, it is recommended to become familiar with numeric_bit, numeric_std and maybe use them in new designs.

The two camps (cont.) If you are using Synopsys version Never include both std_logic_unsigned and std_logic_signed together. This will create too many ambiguities for the compiler. It is best to include std_logic_arith only and declare variables as signed or unsigned explicitly and not rely on the implicit conversions

Either Camp General recommendations Declare vectors as either signed or unsigned when appropriate. The port/signal shows the intention of the designer Easier arithmetic operations and no ambiguity in synthesis/simulation This should be done even at the I/O ports (except at the top-level) For counters, try using constrained integer e.x.: signal counter : integer range 0 to 255; Performance (24-bit counter) integer bit_vector std_logic_vector 22 s 713 ms 31 s 369 ms 32 s 756 ms

Coding Arithmetic Operations in VHDL

Arithmetic Operations Note that /, rem and mod are only supported by numeric_std and not std_logic_arith!

Additions/Subtraction General recommendations Always use signed/unsigned signals for its I/O Result could be one bit wider Sign extend the input if you want the full resolution Otherwise, carry/borrow will be lost Always register the output More pipeline registers could be added if wider adder/subtracter is used Synthesis tools infer and choose the best implementation (ripple carry, CLA, CSA, ..) based on timing/area constraints

Additions/Subtraction (cont.) Registered signed adder with carry signal a : signed(15 downto 0) signal b : signed(15 downto 0) signal c : signed(16 downto 0) p_Add_With_Carry: process( clock ) begin if rising_edge(clock) then c <= resize(a, c'length) + resize(b, c'length); end if; end process p_Add_With_Carry; signal a : signed(15 downto 0) signal b : signed(15 downto 0) signal c : signed(16 downto 0) p_Add_With_Carry: process( clock ) begin if rising_edge(clock) then c <= conv_signed(a, c'length) + conv_signed(b, c'length); end if; end process p_Add_With_Carry; numeric_std std_logic_arith c a b

Multiplication General recommendations Always use signed/unsigned signals for its I/O Result width is the sum of the input widths Most multipliers need to be pipelined Synthesis tools infer and choose the best implementation (Booth, Wallace tree, ...) based on timing/area constraints

Multiplication (cont.) 3-stage pipelined signed multiplier constant DEPTH : positive := 3; signal a : signed(15 downto 0) signal b : signed(10 downto 0) signal c : signed(a'length+b'length-1 downto 0); type Pipe_Type is array(0 to DEPTH-1) of signed(c'range); signal pipe : Pipe_Type; p_Mult_pipe: process( clock ) begin if rising_edge(clock) then pipe <= signed(a * b) & pipe(0 to pipe'length-2); end if; end process p_Mult_pipe; c <= pipe(pipe'length-1); c a b

Divide (Remainder/Modulus) Different algorithms for divide Successive conditional subtract Restoring/non-restoring Fast dividers (carry-propagation free add/sub) SRT (different radix sizes) Most can be pipelined Most synthesis tools do not support divider inference

Square Root Algorithms Restoring/non-restoring CORDIC ...

Trigonometric Functions Algorithms Lookup table based CORDIC ...

http://www.eda.org/vhdl-200x/vhdl-200x-ft

STD.Standard (additions) Proposed additions to STD.Standard New Types boolean_vector, integer_vector, real_vector, time_vector New Operators “??” bit to boolean ex.: (a <= ??b;) = (if b='1' {a<=true} else {a<=false}) “?=” “?/=” “?>” “?>=” “?<” “?<=” shorthand if/else bit/bool e.x.: (a <= b ?= c;) = (if b=c { a<='1' } a<='0'; }) New Functions Boolean reduction (and_reduce, nand_reduce, ...) Boolean array + scalar operators (and, nand, ...) minimum/maximum for primitive types rising_edge, falling_edge for type bit

STD.Textio (additions) Proposed additions to STD.Textio Functions and procedures Read/Write to/from string sread/swrite Binray/Octal/Hex Read/Write bread/bwrite, oread/owrite, hread, hwrite Read/Write for new vector types boolean_vector, integer_vector, real_vector, time_vector String justify and to_string, to_ostring, to_hstring for basic types

IEEE.std_logic_1164 (additions) Proposed additions to IEEE.std_logic_1164 Operators “??” std_logic to boolean “?=” “?/=” “?>” “?>=” “?<” “?<=” shorthand if/else std_logic/std_logic_vector to boolean Functions and procedures to_bit_vector, to_std_logic_vector Shift and rotate for std_logic_vector (sll, srl, rol, ror) Vector-scalar bitwise operations (and, or, ...) Boolean bitwise std_logic -> std_logic Reduction functions for std_logic_vector (or_reduce, ...) Read/Write (decimal, binary, octal, hex) for std_logic_vector to_string, to_bstring, to_ostring, to_hstring

IEEE.numeric_bit_unsigned (new) New unsigned functions/operators for bit_vector Arithmetic operators +, -, *, /, mod, rem Logical operators <, <=, =, /=, =>, > Shift, rotate and resize for bit_vector (unsigned) Maximum, minimum find_lsb, find_lsb Shorthand compare to boolean (?=, ?/=, ...)

IEEE.numeric_std (additions) Proposed additions to IEEE.numeric_std overloaded operators for std_logic and signed/unsigned +, -, bitwise (and, or, ..) New overloads for resize, to_unsigned, and to_signed with a vector as new size New overloads for signed/unsigned input Shorthand conditional operators (?=, ?/=, ...) Shift operators (sla, sra) Functions: maximum, minimum, find_lsb, find_msb Reductions (and_reduce, ...) add_sign, remove_sign, various to_strings, various read/write

IEEE.numeric_std_unsigned (new) New unsigned functions/operators for std_logic_vector Arithmetic operators +, -, *, /, mod, rem Logical operators <, <=, =, /=, =>, > Shift, rotate and resize for std_logic_vector (unsigned) Maximum, minimum find_lsb, find_lsb Shorthand compare to boolean (?=, ?/=, ...)

IEEE.fixed_pkg (new) New fixed-point package Various rounding, saturations styles Implemented as constant, but will use package generics when new VHDL-200x is finalized New Data Types Unsigned/Signed fixed-point (ufixed, sfixed) Decimal point between index 0 and -1 e.x.: sfixed(1, -2) { “xx.xx” -> range [-2.0 .. +1.75] } Operators/Functions (overloads for real/integer and sfixed/ufixed) Abs, +, -, *, /, mod, rem Divide, reciprocal, remainder, modulo, scalb Logical (<, <=, ...) and shorthand logical (?=, ?/=, ...) Shift/rotate, bitwise, reduction, resize, conversion and to_string, from_string, and various read/write

IEEE.float_pkg (new) New floating-point package Various rounding styles, exponent, and fraction widths Implemented as constant, but will use package generics when new VHDL-200x is finalized New Data Types Generic (float), IEEE-754 single precision (float32), IEEE-754 double precision (float64), Long Double (float128) Array of std_logic e.x.: float32 = float(8, -23) {sign+8 exp+24 fract} Operators/Functions (overloads for real/integer and sfixed/ufixed) +, -, *, /, mod, rem Add, subtract, multiply, divide, remainder, modulo, reciprocal, dividebyp2, mac, eq, ne, lt, gt, le, ge, conversion and to_string, from_string, and various read/write

IEEE.float_alg_pkg (new) New floating-point algorithms package Complex add, subtract, multiply, divide, to polar, from polar, sqrt Floating point nr_divide, nr_reciprocal, sqrt, cbrt, inverse_sqrt, exp, log, power_of, ln, **, sin, cos, tan, arcsin, arccos, arctan

Reusable/Generic Code Design considerations Avoid using direct instantiation of primitive components unless at the top, I/O level It is best to put technology dependent instantiations in one file (I/O is recommended) Main concerns Arithmetic operations Memories Other cores

Reusable/Generic Code (cont) Configuration Generic configurations (config_pkg) Constants and types for different technologies/chips Chips specific configuration (config_hill_pkg) Constants for configuring a specific chip Package config_pkg is type TARGET_TYPE is (FPGA, ASIC); type VENDOR_TYPE is (XILINX, IBM, LSI, ...); type XILINX_PARTS is (Virtex2, Virtex4, ...); type IBM_PROCESSES is (G4, G5, ...); type LSI_PROCESSES is (Flex, Gflex, ...); End Package config_pkg; Package hill_config_pkg is -- Chip specific parameters constant DEVICE_ID : ... = ...; constant HAS_CLOCK_ERROR : boolean := TRUE; constant VITERBI_TRACE_BACK : positive := ...; constant HAS_FLASH : boolean := TRUE; constant FLASH_DATA_SIZE : positive := 16; End Package hill_config_pkg;

Reusable/Generic Code (cont) Simple Arithmetic Operations (+, -, *) Write behavioral inferred code (signed/unsigned) Note: / and rem could be coded in RTL Complex arithmetic or cores (/, mod, rem, sqrt, ...) Write a wrapper and instantiate the appropriate technology dependent component a <= b * c; d <= a + d; g_XILINX_V2: if ( TARGET=XILINX_V2 ) generate u_div: generic_divider generic map (...) port map (...); end generate; g_IBM_G5: if ( TARGET=IBM_G5 ) generate u_div: DW_DIV port map (....); end generate;

Reusable/Generic Code (cont) Memories Create a wrapper for each memory Instantiate technology dependent memory based on a generic passed to the wrapper Entity memory is generic (TARGET : TARGET_TYPE ); ... begin g_Xilinx_V2: if ( TARGET=X_V2 ) generate u_mem : block_memory_RW generic map (...) port map (...); end generate; g_LSI_GFlex: if ( TARGET=LSI_GFlex ) generate u_mem : m1r2d_xyz port map (...); end generate; End Entity memory;

Conclusion Become familiar with VHDL standard packages and libraries Use signed/unsigned for arithmetic operations Write generic technology independent code Use wrapper for memories, technology dependent cores

VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions

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VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions