VHDL-Behavioral-Programs-Structure of VHDL
- 1. Review: Structure of VHDL –explanation & Syntax Behavioral Modelling-with examples Kongunadu College of Engineering & Technology VHDL 1
- 2. Structure of VHDL module The main components of a VHDL description consists of following kinds of declarations: Package Entity Architecture Configuration Kongunadu College of Engineering & Technology VHDL 2
- 3. Entity Declaration It gives the specification of input/output signals to external circuitry. An entity is modeled using an entity declaration and at least one architecture body. Entity gives interfacing between device and the other peripherals. Syntax: entity entity_name is port( signal_names: mode signal_type; signal_names: mode signal_type; . . . signal_names: mode signal_type); end entity_name; Kongunadu College of Engineering & Technology VHDL 3
- 4. Architecture It specifies the behavior, functionality, interconnections or relationship between inputs and outputs. It is the actual description of the design. An architecture consists of two portions: architecture declaration and architecture body An architecture body specifies the internal details of the entity. set of concurrent assignment statements(to represent dataflow) set of interconnected components(to represent structure) set of sequential assignment statements(to represent behavior) Kongunadu College of Engineering & Technology VHDL 4
- 5. Contd… Syntax: Architecture architecture_name of entity_name is Declarations begin concurrent statements; sequential statements; end architecture_name; Kongunadu College of Engineering & Technology VHDL 5
- 6. Configuration declaration It may be used to associate particular design entities to component instances in a hierarchical design, or to associate a particular architecture to an entity. Package declaration It is a convenient mechanism to store and share the declarations that are common across many design units A package is represented by: Package declaration and Package body Kongunadu College of Engineering & Technology VHDL 6
- 7. Contd… Syntax for package declaration: PACKAGE package_name IS Type declarations Subtype declarations Constant declarations Signal declarations Use clauses END package_name; Syntax for package body: Package body package_name is Subprogram bodies Subprogram declarations Type and subtype declarations File and alias declarations Use clauses End package_name; Kongunadu College of Engineering & Technology VHDL 7
- 8. Behavioral Modelling It is method of directly describe the behavior or the functionality of a circuit. In VHDL, the behavior of the entity is expressed using sequentially executed, procedural code. The key mechanism used to model the behavior of the entity is a process statement. Kongunadu College of Engineering & Technology VHDL 8
- 9. Examples of Behavioral modelling Write the VHDL code half adder in behavioral model. entity half_add is Port(A,B: in bit; Sum,cout:out bit); end half_add; architecture adder of half_add is begin sum<= A XOR B; cout<= A and B; end adder; Kongunadu College of Engineering & Technology VHDL 9
- 10. Contd… Write the VHDL code full adder in behavioral model. entity full_add is Port(A,B,Cin: in bit; Sum,cout:out bit); end full_add; architecture adder of full_add is begin Process(A,B,Cin) begin sum<= A xor B xor Cin; cout<= (A and B) or (Cin and A) or (Cin and B) ; end process; end adder; Kongunadu College of Engineering & Technology VHDL 10
- 11. Contd… Write the VHDL code for a logical gate which gives high output only when both the inputs are high. Library ieee; Use ieee.std_logic_1164.all; Entity AND_G is Port(A,B :in bit; Y :out bit); End AND_G; Architecture AND of AND_G is Begin Q<=A and B; End AND; Kongunadu College of Engineering & Technology VHDL 11
- 12. Contd… Write VHDL behavioral model for D flip flop. Library ieee; Use ieee.std_logic_1164.all; Entity DFF is Port(D,Clock :in std_logic; Q :out std_logic); End DFF; Architecture behavior of DFF is Begin If Clock’event and clock=’1’ then Q<=D; End if; End process; End behavior; Kongunadu College of Engineering & Technology VHDL 12
- 13. Conclusion & References Through this presentation we have learned about the basic structure of VHDL with the syntax of all its components Also the behavioral model of VHDL is discussed with examples. References: Kongunadu College of Engineering & Technology VHDL 13 1. Mandal, “Digital Electronics Principles & Application, McGraw Hill Edu, 2013. 2. William Keitz, Digital Electronics-A Practical Approach with VHDL, Pearson, 2013. 3. Thomas L.Floyd, ‘Digital Fundamentals’, 11th edition, Pearson Education, 2015. 4. Charles H.Roth, Jr, Lizy Lizy Kurian John, ‘Digital System Design using VHDL, Cengage,2013. 5. D.P.Kothari,J.S.Dhillon, ‘Digital circuits and Design’,Pearson Education, 2016. 6. A.P.Godse., Dr.D.A.Godse, ‘Digital Logic Circuits’ , Technical Publications Third Edition 2016 7. Other Web Sources