4. Types of Field Effect Transistors
(The Classification)
» JFET
MOSFET (IGFET)
n-Channel JFET
p-Channel
JFET
n-Channel
EMOSFET
p-Channel
EMOSFET
Enhancement
MOSFET
Depletion
MOSFET
n-Channel
DMOSFET
p-Channel
DMOSFET
FET
MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor)
Primary component in high-density VLSI chips such as memories and microprocessors
JFET (Junction Field-Effect Transistor)
Finds application especially in analog and RF circuit design
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Metal Oxide Semiconductor(MOS)
• Advantages of FET over conventional Transistors
• Unipolar device i. e. operation depends on only one type of charge carriers (h or e)
• Voltage controlled Device (gate voltage controls drain current)
• Very high input impedance (109-1012 )
• Source and drain are interchangeable in most Low-frequency applications
• Low Voltage Low Current Operation is possible (Low-power consumption)
• Less Noisy as Compared to BJT
• No minority carrier storage (Turn off is faster)
• Very small in size, occupies very small space in ICs
7. Switch Model of PMOS Transistor
Gate
Source
(of carriers)
Drain
(of carriers)
GS
| V |
| VGS | > | VDD – | VT | | | VGS | < | VDD – |VT| |
Open (off) (Gate = ‘1’) Closed (on) (Gate = ‘0’)
Ron
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8. MOS transistors Symbols
D
G
S
NMOS Enhancement
D
S
NMOS Depletion
G
G
S
D D
S
NMOS with
Bulk Contact
G
PMOS Enhancement
B
Channel
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9. MOSFET Circuit Symbols
• (g) and (i) are the most
commonly used symbols
in VLSI logic design.
• MOS devices are
symmetric.
• In NMOS, n+ region at
higher voltage is the
drain.
• In PMOS p+ region at
lower voltage is the drain
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10. The NMOS Transistor Cross Section
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n areas have been doped with donor ions
(arsenic) of concentration ND - electrons are
the majority carriers
majority carriers
Gate oxide
n+
Source Drain
p substrate
Bulk (Body)
p areas have been doped with acceptor ions
(boron) of concentration NA - holes are the
p+ stopper
Field-Oxide
(SiO2)
n+
Polysilicon
Gate
L
W
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Carriers and Current
• Carriers always flow from the Source to Drain
• NMOS: Free electrons move from Source to
Drain.
– Current direction is from Drain to Source.
• PMOS: Free holes move from Source to
Drain.
– Current direction is from Source to Drain.
–
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The MOSFET Channel
• Under certain conditions, a thin channel can
be formed right underneath the Silicon-
Dioxide insulating layer, electrically connecting
the Drain to the Source. The depth of the
channel (and hence its resistance) can be
controlled by the Gate’s voltage. The length of
the channel (shown in the figures above as L)
and the channel’s width W, are important
design parameters.
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REGION OF OPERATION
CASE-1 (No Gate Voltage)
• Two diodes back to back exist in series.
• One diode is formed by the pn junction
between the n+ drain region and the p-type
substrate
• Second is formed by the pn junction between
the n+ source region and the p-type substrate
• These diodes prevent any flow of the current.
• There exist a very high resistance.
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REGION OF OPERATION
Creating a channel
• Apply some positive voltage on the gate
terminal.
• This positive voltage pushes the holes
downward in the substrate region.
• This causes the electrons to accumulate under
the gate terminal.
• At the same time the positive voltage on the
gate also attracts the electrons from the n+
region to accumulate under the gate terminal.
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REGION OF OPERATION
Creating a channel
• When sufficient electrons are accumulated under the
gate an n-region is created, connecting the drain and
the source
• This causes the current to flow from the drain to
source
• The channel is formed by inverting the substrate
surface from p to n, thus induced channel is also called
as the inversion layer.
• The voltage between gate and source called vgs at
which there are sufficient electron under the gate to
form a conducting channel is called threshold voltage
Vth.
21. Formation of Channel
• First, the holes are
repelled by the
positive gate voltage,
leaving behind
negative ions and
forming a depletion
region. Next,
electrons are attracted
to the interface,
creating a channel
(“inversion layer”).
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22. 24
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MOS Transistor Current direction
• The source terminal of an n-channel(p-channel)
transistor is defined as whichever of the two terminals
has a lower(higher) voltage.
• When a transistor is turned ON, current flows from the
drain to source in an n-channel device and from source
to drain in a p-channel transistor.
• In both cases, the actual carriers travel from the source
to drain.
• The current directions are different because n-channel
carriers are negative, whereas p-channel carriers are
positive.
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REGION OF OPERATION
Applying small Vds
• Now we applying some small voltage between
source and drain
• The voltage Vds causes a current to flow from
drain to gate.
• Now as we increase the gate voltage, more
current will flow.
• Increasing the gate voltage above the threshold
voltage enhances the channel, hence this mode is
called as enhancement mode operation.
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Operation – nMOS Transistor
• Accumulation Mode - If Vgs < 0, then an
electric field is established across the
substrate.
• Depletion Mode -If 0<Vgs< Vtn, the region
under gate will be depleted of charges.
• Inversion Mode – If Vgs > Vtn, the region
below the gate will be inverted.
32. Voltage-Dependent Resistor
• The inversion channel
of a MOSFET can be
seen as a resistor.
• Since the charge
density inside the
channel depends on
the gate voltage, this
resistance is also
voltage-dependent.
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33. Channel Potential Variation
• Since there’s a
channel resistance
between drain and
source, and if drain is
biased higher than
the source, then the
potential between
gate and channel will
decrease from
source to drain.
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34. Channel Pinch-Off
• As the potential
difference between drain
and gate becomes more
positive, the inversion
layer beneath the
interface starts to pinch
off around drain.
• When VD s> VGs - Vth,
the channel at drain
totally pinches off, and
when VD s< VGs - Vth,
the channel length starts
to decrease.
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38. Transistor in Saturation Mode
S
D
G
VGS
VDS > VGS - VT
ID
VGS - VT
- +
n+ n+
Assuming VGS > VT
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VDS
Pinch-off
B
The current remains constant (saturates).
39. During “pinchoff”
Does this mean that the current i =0 ? Actually, it does not. A MOSFET
that is “pinched off” at the drain end of the channel still conducts current:
The large E in the depletion region surrounding the drain will sweep
electrons across the end of the pinched off channel to the drain.
This is very similar to the operation of the BJT. For an npn BJT, the electric
field of the reversed biased CBJ swept electrons from the base to the
collector regions.
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43. Enhancement-Mode PMOS
Transistors: Structure
• p-type source and drain
regions in n-type substrate.
• vGS < 0 required to create p-
type inversion layer in channel
region
• For current flow, vGS < vTP
• To maintain reverse bias on
source-substrate and drain-
substrate junctions, vSB <
0 and vDB < 0
• Positive bulk-source potential
causes VTP to become more
negative
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45. Depletion-Mode MOSFETS
• NMOS transistors with
• Ion implantation process
is used to form a built-in
n-type channel in the
device to connect source
and drain by a resistive
channel
• Non-zero drain current
for vGS = 0; negative vGS
required to turn device
off.
VTN
0
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Oxidation
Formation of silicon dioxide layer on the surface of Si wafer
1. protects surface from contaminants
2. forms insulating layer between conductors
3. form barrier to dopants during diffusion or ion implantation
4. grows above and into silicon surface
Dry oxidation: lower rate and higher quality
Wet oxidation: higher rate and lower quality
1. SiO2 is an extremely hard protective coating & is unaffected
by almost all reagents except by hydrochloric acid. Thus it
stands against any contamination.
2. By selective etching of SiO2, diffusion of impurities through
carefully defined through windows in the SiO2 can be
accomplished to fabricate various components.
51. Oxidation
The silicon wafers are stacked up in a quartz boat & then
inserted into quartz furnace tube. The Si wafers are raised
to a high temperature in the range of 950 to 1150oC & at
the same time, exposed to a gas containing O2 or H2O or
both. The chemical action is
Si + 2H2O-----------> Si O2+ 2H2 (Wet )
Si + O2 -------------> SiO2 (Dry )
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52. Photolithograph
y
• Coat wafer with photoresist
(PR)
• Shine UV light through mask
to selectively expose PR
• Use acid to dissolve exposed
PR
• Now use exposed areas for
– Selective doping
– Selective removal of material
under exposed PR
Wafer
UV Light
Mask
Photoresist
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53. Adding Materials
• Add materials on top of
silicon
– Polysilicon
– Metal
– Oxide (SiO2) - Insulator
• Methods
– Chemical deposition
– Sputtering (Metal ions)
– Oxidation
Silicon
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Added Material
(e.g. Polysilicon)
54. Oxide (Si02) - The Key Insulator
Silicon Wafer Silicon Wafer
• Thin Oxide
– Add using chemical deposition
– Used to form gate insulator & block active areas
• Field Oxide (FOX) - formed by oxidation
– Wet (H20 at 900oC - 1000oC) or Dry (O2 at 1200oC)
– Used to insulate non-active areas
SiO2 Thin Oxide FOX SiN / SiO2
FOX
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55. Patterning Materials using
Photolithography
• Add material to wafer
• Coat with photoresist
• Selectively remove
photoresist
• Remove exposed
material
• Remove remaining
PR
Silicon
Added Material
(e.g. Polysilicon)
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56. Diffusion
• Introduce dopant via epitaxy or
ion implant e.g. Arsenic (N),
Boron (P)
• Allow dopants to diffuse at
high
temperature
• Block diffusion in selective areas
using oxide or PR
• Diffusion spreads both vertically,
horizontally
Silicon
Diffusion
Blocking Material
(Oxide)
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57. Ion Implantation
180 kV
Resolving
Aperture
Ion Source
Equipment Ground
Acceleration Tube
90° Analyzing
Magnet Terminal
Ground
20 kV
Focus Neutral beam
and
beam path
gated
Beam trap and
gate plate
Wafer in wafer
process chamber
X - axis
scanner
Neutral beam trap Y - axis
and beam gate
scanner
Gases
Ar
AsH3
Slide
B11F3 *
He
N2
PH3
SiH4
SiF
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Solids
Ga
In
Sb
Liqui
ds
Al(
C
Process Conditions
Flow Rate: 5 sccm
Pressure: 10-5
Torr
Accelerating Voltage:
5
to 200 keV
58. 6/3/2015
Slide 60
Metallization
• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires
p substrate
Metal
Thick field oxide
n well
n+
n+ n+
p+
p+
p+
Metal
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nMOS fabrication steps
1.Processing is carried out on a thin wafer cut from a single crystal of silicon of high purity into which the
required p-impurities are introduced as the crystal is grown.
2.A layer of silicon dioxide (Si02) is grown all over the surface of the wafer to protect the surface, act as a
barrier to dopants during processing, and provide a generally insulating substrate on to which other layers
may be deposited and patterned.
3.The surface is now covered with a photoresist which is deposited onto the wafer and spun to achieve an
even distribution of the required thickness.
4.The photoresist layer is then exposed to ultraviolet light through a mask which defines those regions into
which diffusion is to take place together with transistor channels.
5.These areas are subsequently readily etched away together with the underlying silicon dioxide so that the
wafer surface is exposed in the window defined by the mask.
6.The remaining photoresist is removed and a thin layer of Si02 is grown over the entire chip surface and then
polysilicon is deposited on top of this to form the gate structure.
7.Further photoresist coating and masking allows the polysilicon to be patterned (as shown in Step 6) and
then the thin oxide is removed to expose areas into which
8.Thick oxide (Si02) is grown over all again and is then masked with photoresist and etched to expose
selected areas of the polysilicon gate and the drain and source areas where connections (i.e. contact cuts)
are to be made.
9.The whole chip then has metal (aluminium) deposited over its surface. This metal layer is then masked
and etched to form the required interconnection pattern.
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CMOS FABRICATION
• There are a number of approaches to CMOS
fabrication, including the p-well, the n-well,
the twin-tub, and the silicon-on-insulator
processes.
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The p-well Process
In primitive terms, the structure consists of an n-
type substrate in which p-devices may
be formed by suitable masking and diffusion
and, in order to accommodate n-type devices,
a deep p-well is diffused into the n-type
substrate as shown.
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The p-well CMOS fabrication
In all other respects-masking, patterning, and diffusion-the process is similar to
nMOS fabrication. In summary, typical processing steps are:
• Mask 1 - defines the areas in which the deep p-well diffusions are to take place.
•Mask 2 - defines the thinox regions, namely those areas where the thick oxide is
to be stripped and thin oxide grown to accommodate p- and n-transistors and wires.
• Mask 3 - used to pattern the polysilicon layer which is deposited after the thin
oxide.
•Mask 4 - A p-plus mask is now used (to be in effect "Anded" with Mask 2) to define
all areas where p-diffusion is to take place.
•Mask 5 - This is usually performed using the negative form of the p-plus mask and
defines those areas where n-type diffusion is to take place.
• Mask 6 - Contact cuts are now defined.
• Mask 7 - The metal layer pattern is defined by this mask.
Mask 8 - An overall passivation (overglass) layer is now applied and Mask 8 ts
needed to define the openings for access to bonding pads.
71. The n-well Process
• As indicated earlier, although the p-well process is widely used, n-well fabrication
has also gained wide acceptance, initially as a retrofit to nMOS lines.
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The twin-tub-Tub Process
A logical extension of the p-well and n-well approaches is
the twin-tub fabrication process.
Here we start with a substrate of high resistivity n-type
material and then create both .. n-well and p-well
regions. Through this process it is possible to preserve the
performance of n-transistors without compromising the
p-transistors. Doping control is more readily achieved
and some relaxation in manufacturing tolerances results.
This is particularly important as far
as latch-up is concerned.
73. Vin
Vout
VSS
VDD
Twin-tub structure
( A logical extension of the p-well and n-
well)
Polysilicon
Oxide
n-diffusion
P-
diffusion
n substrate
n well p well
Epitaxial
layer
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74. Bipolar compatible CMOS(Bi-CMOS) technology:
Introduced in early 1980s
Combines Bipolar and CMOS logic
Low power dissipation
High packing density
High speed
High output
drive
High Noise Margin High transconductance
(gm)
High input impedance
Bi-CMOS
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75. Features
The objective of the Bi-CMOS is to combine bipolar and CMOS so as to
exploit the advantages of both the technologies.
Today Bi-CMOS has become one of the dominant technologies used for
high speed, low power and highly functional VLSI circuits.
The process step required for both CMOS and bipolar are almost similar
The primary approach to realize high performance Bi-CMOS devices is
the
addition of bipolar process steps to a baseline CMOS process.
The Bi-CMOS gates could be used as an effective way of speeding up
the VLSI circuits.
The applications of Bi-CMOS are vast.
Advantages of bipolar and CMOS circuits can be retained in Bi-
CMOS chips.
76. Higher switching speed
Higher current drive per unit area, higher gain
Generally better noise performance and better high
frequency characteristics
Improved I/O speed (particularly significant with the growing
importance
of package limitations in high speed systems).
high power dissipation
lower input impedance (high drive current)
low packing density
low delay sensitivity to load
It6
/
3
is/
2
0
e1
5
ssentially unidirectional.
Characteristics of Bipolar Technology
78
77. 6/3/2015 79
Lower static power dissipation
Higher noise margins
Higher packing density
High yield with large integrated complex functions
High input impedance (low drive current)
Scalable threshold voltage
High delay load sensitivity
Low output drive current (issue when driving large capacitive loads)
Bi-directional capability (drain & source are interchangeable)
A near ideal switching device,
Low gain
Characteristics of CMOS
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CMOS process
process
1 . N-well
step)
3. PMOS source
and drain
4. NMOS source
and drain
BI-POLAR
1. n+ sub-collector
2. P base doping(extra
3. p+ base contact
4. n+ emitter
Bi-CMOS FABRICATION PROCESS
80. BJT Processing
1. Implantation of the buried n+ layer
2. Growth of the epitaxial layer
3. p+ isolation diffusion
4. Base p-type diffusion
5. Emitter n+ diffusion
8. Metal deposition and etching
9. Passivation and bond pad opening
6. p+ ohmic contact
7. Contact etching
p-substrate
n+ buried layer
p-base layer
n+ layer
n+ layer p+ layer
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81. BJT Processing
1. Implantation of the buried n+ layer
2. Growth of the epitaxial layer
3. p+ isolation diffusion
4. Base p-type diffusion
5. Emitter n+ diffusion
6. p+ ohmic contact
7. Contact etching
8. Metal deposition and etching
p-substrate
83
9. Passivation and bond pad opening
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82. BJT Processing
1. Implantation of the buried n+ layer
2. Growth of the epitaxial layer
3. p+ isolation diffusion
4. Base p-type diffusion
5. Emitter n+ diffusion
6. p+ ohmic contact
7. Contact etching
8. Metal deposition and etching
n+ buried layer
9. Passivation and bond pad opening
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n epi layer
p-substrate
83. BJT Processing
1. Implantation of the buried n+ layer
2. Growth of the epitaxial layer
3. p+ isolation diffusion
4. Base p-type diffusion
5. Emitter n+ diffusion
6. p+ ohmic contact
7. Contact etching
8. Metal deposition and etching
n+ buried layer
p
+
p-substrate
85
9. Passivation and bond pad opening
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isolation
layer
p
+
isolation
layer
84. BJT Processing
1. Implantation of the buried n+ layer
2. Growth of the epitaxial layer
3. p+ isolation diffusion
4. Base p-type diffusion
5. Emitter n+ diffusion
8. Metal deposition and etching
6. p+ ohmic contact
7. Contact etching
n+ buried layer
p
+
isolation
layer
p
+
isolation
layer
p-base
layer
p-substrate
86
9. Passivation and bond pad opening
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85. BJT Processing
1. Implantation of the buried n+ layer
2. Growth of the epitaxial layer
3. p+ isolation diffusion
4. Base p-type diffusion
5. Emitter n+ diffusion
8. Metal deposition and etching
6. p+ ohmic contact
7. Contact etching
n+ buried layer
p
+
isolation
layer
p
+
isolation
layer
p-base layer
n+ layer
p-substrate
87
9. Passivation and bond pad opening
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n+ layer
86. BJT Processing
1. Implantation of the buried n+ layer
2. Growth of the epitaxial layer
3. p+ isolation diffusion
4. Base p-type diffusion
5. Emitter n+ diffusion
8. Metal deposition and etching
6. p+ ohmic contact
7. Contact etching
n+ buried layer
p
+
isolation
layer
p
+
isolation
layer
p-base layer
n+ layer
p-substrate
88
9. Passivation and bond pad opening
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n+ layer p+ layer
87. BJT Processing
1. Implantation of the buried n+ layer
2. Growth of the epitaxial layer
3. p+ isolation diffusion
4. Base p-type diffusion
5. Emitter n+ diffusion
8. Metal deposition and etching
6. p+ ohmic contact
7. Contact etching
n+ buried layer
p+ isolation layer
p-base layer
n+ layer
n+ layer p+ layer
p-substrate
89
9. Passivation and bond pad opening
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88. BJT Processing
1. Implantation of the buried n+ layer
2. Growth of the epitaxial layer
3. p+ isolation diffusion
4. Base p-type diffusion
5. Emitter n+ diffusion
8. Metal deposition and etching
6. p+ ohmic contact
7. Contact etching
n+ buried layer
p+ isolation layer
p-base layer
n+ layer
n+ layer p+ layer
p-substrate
90
9. Passivation and bond pad opening
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89. BJT Processing
1. Implantation of the buried n+ layer
2. Growth of the epitaxial layer
3. p+ isolation diffusion
4. Base p-type diffusion
5. Emitter n+ diffusion
8. Metal deposition and etching
6. p+ ohmic contact
7. Contact etching
n+ buried layer
p+ isolation layer
p-base layer
n+ layer
n+ layer p+ layer
p-substrate
91
9. Passivation and bond pad opening
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94. NMOS PMOS
S G D S G D
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NPN-BJT
C B E
N Plus Buried Layer
N-Well (Collector)
N-
Diff
N-
Diff
P-Diff P-Diff N-Plus
Emitter
P-SUBSTRATE
P-
EPITAXY
BICMOS STRUCTURE
96. THROUGH THE WINDOW N TYPE IMPURITIES IS HEAVILY DOPED
N Plus Buried Layer
P-SUBSTRATE
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P-SUBSTRATE
A WINDOW IS OPENED THROUGH OXIDE LAYER
98. P-
EPITAXY
THE ENTIRE SURFACE IS COVERED WITH OXIDE LAYER AND TWO WINDOWS
ARE OPENED THROUGH THE OXIDE LAYER
N Plus Buried Layer
P-SUBSTRATE
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99. THROUGH THE TWO WINDOWS N-TYPE IMPURITIES ARE DIFFUSED TO
FORM N-WELLS
N-Well
N-Well (Collector)
P-
EPITAXY
N Plus Buried Layer
P-SUBSTRATE
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100. THREE WINDOWS ARE OPENED THROUGH THE OXIDE LAYER , IN THESE
THREE WINDOWS THREE ACTIVE DEVICES NMOS,PMOS AND NPN BJT
ARE FORMED
N-Well
N-Well (Collector)
P-
EPITAXY
N Plus Buried Layer
P-SUBSTRATE
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101. THE ENTIRE SURFACE IS COVERED WITH THINOX AND POLYSILICON
AND ARE PATTERNED TO FORM THE GATE TERMINALS OF THE NMOS
AND PMOS
N-Well
N-Well (Collector)
P-
EPITAXY
N Plus Buried Layer
P-SUBSTRATE
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102. THROUGH THE 3RD WINDOW THE P-IMPURITIES ARE MODERATELY
DOPED TO FORM THE BASE TERMINAL OF BJT
N-WELL ACTS LIKE THE COLLECTOR TERMINAL
N-Well P-Base
N-Well (Collector)
P-
EPITAXY
N Plus Buried Layer
P-SUBSTRATE
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103. N-
Diff
N-Well P-Base
N-Well (Collector)
P-
EPITAXY
N Plus Buried Layer
P-SUBSTRATE
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N-
Diff
N-Plus
Emitter
THE N-TYPE IMPURITES ARE HEAVILY DOPED TO FORM
1.SOURCE AND DRAIN REGION OF NMOS
2.EMITTER TERMINAL OF BJT
3.AND INTO NWELL COLLECTOR REGION FOR CONTACT PURPOSE
104. N-
Diff
N-Well P-Base
N-Well (Collector)
P-
EPITAXY
N Plus Buried Layer
P-SUBSTRATE
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N-
Diff
P-Diff P-Diff N-Plus
Emitter
THE P-TYPE IMPURITES ARE HEAVILY DOPED TO FORM
1.SOURCE AND DRAIN REGION OF PMOS
2.AND INTO P-BASE REGION FOR CONTACT PURPOSE
106. N-Well
N-Well (Collector)
P-
EPITAXY
N Plus Buried Layer
P-SUBSTRATE
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N-
Diff
N-
Diff
P-Diff P-Diff
P-Base
N-Plus
Emitter
THE ENTIRE SURFACE IS COVERED WITH THICK OXIDE LAYER AND IS
PATTERNED FOR CONTACT CUTS
107. NMOS PMOS
S G D S G D
N-Well (Collector)
P-
EPITAXY
N Plus Buried Layer
P-SUBSTRATE
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NPN-BJT
C B E
N-
Diff
N-
Diff
P-Diff P-Diff N-Plus
Emitter
METAL CONTACTS ARE FORMED
