zeroth Review ppt.pptx Its about design and comparison of 4×4 bit multiples utilising CMOS 45nm and Finfet technology

zeroth Review ppt.pptx Its about design and comparison of 4×4 bit multiples utilising CMOS 45nm and Finfet technology

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  RAGHU ENGINEERING COLLEGE (AUTONOMOUS) DEPARTMENTOF ELECTRONICS AND COMMUNICATION ENGINEERING TEAM MEMBERS: 1. PRANJALI MUTYALA : 223J1A0483 2. V RUCHITHA : 223J5A0415 3. P HAREESH : 223J1A0493 4. S PREM KUMAR : 223J1A04A8 SECTION - F BATCH NO – F17 UNDER THE ESTEEMED GUIDANCE OF: DR. SRINIVAS GUPTA Raghu Engineering College, Visakhapatnam Design And Comparison of 4x4 Bit Multipliers Utilizing CMOS 45nm And FinFET Technology
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  CONTENTS Raghu Engineering College,Visakhapatnam Dept. of ECE INTRODUCTION OBJECTIVES ABSTRACT LITERATURE REVIEW REFERENCE
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  INTRODUCTION  Digital multipliersare key components in DSP, image processing, and other applications where multiplication speed and power matter.  This study compares two multiplier architectures ripple carry and array multipliers implemented in 45nm CMOS and 18nm FINFET technologies.  We compare two 4*4 multipliers the Ripple carry multiplier and the Array multipler. The goal is to find the best balance between low power and high performance. Dept. of ECE Raghu Engineering College, Visakhapatnam
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  Objectives  Design 4*4Ripple Carry and array multipliers in cmos 45nm and FinFET 18nm.  Evaluate and Compare Power dissipation ,delay time, and power delay product across technologies.  To evaluate how different architecture affect performance in terms of speed and efficiency. Dept. of ECE Raghu Engineering College, Visakhapatnam
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  Abstract  The paperpresents simulation analysis of 4*4 bit multipliers implemented in CMOS and FinFET, focusing on ripple carry and array architectures.  Results show array multipliers have low delay but higher power and ripple carry multipliers have low power but high delay.  The Study aids optimized multiplier design for modern digital circuits.  FINFET provides better leakage control and energy efficiency compared to CMOS. Dept. of ECE Raghu Engineering College, Visakhapatnam
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  Literature Review  Arraymultipliers deliver low delay due to parallel processing , ripple carry multipliers favour low power by simple design.  CMOS 45nm is a mature and widely used technology ,while FINFET 18nm offers better control over leakage and performance.  Instead of Ripple carry adder we have to use carry look adder and another tech node will simulate. Dept. of ECE Raghu Engineering College, Visakhapatnam
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  References J.-F. Lin, C.-Y.Chan, and S.-W. Yu, “Novel low voltage and low power array multiplier design for IoT applications,” Electronics (Basel), vol. 8, no. 12, p. 1429, 2019.  N. H. E. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective. Addison-Wesley, 2010. R. A. Aroca, A. Tomkins, Y. Doi, T. Yamamoto, and S. P. Voinigescu, “Circuit performance characterization of digital 45-nm CMOS technology for applications around 110 GHz,” in 2008 IEEE Symposium on VLSI Circuits, 2008. K. Sharma, S. Thakur, M. Elangovan, and A. Sachdeva, “Low power FinFEzT based boost converter design ‐ using dynamic threshold body biasing technique,” Int. J. Numer. Model., vol. 37, no. 2, 2024. G. Rana, K. Sharma, and A. Sharma, “Comparative Analysis of FinFET and CMOS based Adiabatic ECRL Technique,” in 2023 International Conference on Sustainable Computing and Smart Systems (ICSCSS), IEEE, 2023, pp. 1179– 1182 A. Garg and G. Joshi, “Gate diffusion input based 4 bit Vedic multiplier design,” IET Circuits Devices ‐ Syst., vol. 12, no. 6, pp. 764–770, 2018. Dept. of ECE Raghu Engineering College, Visakhapatnam