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Taruna Reddy

Rob van Blommestein

Rimpy Chugh

Quantum Computing: How Advances May Reshape Our Understanding of the World

BLOG Jul 29, 2025/4 min read

BLOG

Quantum Computing: How Advances May Reshape Our Understanding of the World

By Synopsys Editorial Staff

Tags: Test, Chip Design Insights, Quantum Computing, Simulation, Design, Verification

Automotive Reckoning: Industry Leaders Discuss the Race to Redefine Car Development

BLOG Jul 15, 2025/3 min read

BLOG

Automotive Reckoning: Industry Leaders Discuss the Race to Redefine Car Development

By Synopsys Editorial Staff

Tags: Chip Design Insights, Simulation, Design, Automotive, Verification, Virtual Prototyping

Driving the Future of Automotive: How Synopsys and Tata Elxsi Are Powering Electronics Digital Twin (eDT) Adoption

BLOG Jul 11, 2025/2 min read

BLOG

Driving the Future of Automotive: How Synopsys and Tata Elxsi Are Powering Electronics Digital Twin (eDT) Adoption

By Chahinez Hamlaoui, Marc Serughetti

Tags: Test, Chip Design Insights, Simulation, Design, Automotive, Verification, Virtual Prototyping

RTL Signoff vs. Functional Signoff: What’s the Difference?

BLOG Jul 01, 2025/5 min read

BLOG

RTL Signoff vs. Functional Signoff: What’s the Difference?

By Bradley Geden, Manoz Palaparthi

Tags: Verification Central, Multi-Die, RTL Synthesis, Static & Formal Verification, AI & Machine Learning, Debug, Physical Verification, Test, Simulation, Energy-Efficient SoCs, Signoff, Chip Design Insights, Design, Verification, Formal Verification

Using Synopsys VSO.ai to Accelerate Synopsys VIP and IP Coverage

BLOG Apr 04, 2025/3 min read

BLOG

Using Synopsys VSO.ai to Accelerate Synopsys VIP and IP Coverage

By Taruna Reddy

Tags: AI & Machine Learning, Debug, Simulation, Verification IP, Verification

Synopsys HAPS-200 and ZeBu-200 Expand the Industry’s Highest Performance Hardware-Assisted Verification Portfolio

BLOG Feb 13, 2025/5 min read

BLOG

Synopsys HAPS-200 and ZeBu-200 Expand the Industry’s Highest Performance Hardware-Assisted Verification Portfolio

By Frank Schirrmeister

Tags: Chip Design Insights, Simulation, Design, Emulation, Verification, Virtual Prototyping

BLOG Sep 10, 2024/2 min read

BLOG

The Journey of Coverage Closure

By Taruna Reddy

Tags: Verification Central, AI & Machine Learning, Simulation, Verification

Interactive Debugging: Reduce Your Simulation Debug Turnaround Time

BLOG May 09, 2024/3 min read

BLOG

Interactive Debugging: Reduce Your Simulation Debug Turnaround Time

By Vita Liao

Tags: Verification Central, Debug, Simulation, Verification

Running X-Propagation with Low-Power Simulation

BLOG Nov 21, 2023/5 min read

BLOG

Running X-Propagation with Low-Power Simulation

By Manas Ranjan Raiguru

Tags: Verification Central, Simulation, Verification

Streamline Projects with Verdi and VCS Coverage Tools

BLOG Jul 12, 2023/2 min read

BLOG

Streamline Projects with Verdi and VCS Coverage Tools

By Taruna Reddy

Tags: Verification Central, Debug, Simulation, Verification, Formal Verification

How Imparé Leverages Chip Design Verification in the Cloud

BLOG May 03, 2023/6 min read

BLOG

How Imparé Leverages Chip Design Verification in the Cloud

By Rob van Blommestein

Tags: Customer Spotlight, Cloud, Debug, Chip Design Insights, Simulation, Verification

How to Get High-Performance Simulation with Predictable Capacity Uplift in the Cloud

BLOG Mar 07, 2023/6 min read

BLOG

How to Get High-Performance Simulation with Predictable Capacity Uplift in the Cloud

By Meghana Bellumori

Tags: Cloud, Product Spotlight, Chip Design Insights, Simulation, Verification

Enhancing Chip Design Simulation with AI

BLOG Feb 15, 2023/4 min read

BLOG

Enhancing Chip Design Simulation with AI

By Taruna Reddy

Tags: AI & Machine Learning, Product Spotlight, Debug, Chip Design Insights, Simulation, Verification

How to Achieve 2X Faster Waveform Dumping in Synopsys Verdi with VCS

BLOG Dec 15, 2022/2 min read

BLOG

How to Achieve 2X Faster Waveform Dumping in Synopsys Verdi with VCS

By Taruna Reddy

Tags: Verification Central, Debug, Simulation, Verification

How Formal Verification Tools Enhance SoC Simulation Coverage

BLOG Nov 20, 2022/4 min read

BLOG

How Formal Verification Tools Enhance SoC Simulation Coverage

By Jin Zhang

Tags: Product Spotlight, Chip Design Insights, Simulation, Verification, Formal Verification

How to Protect Advanced Chip Designs from Security Breaches

BLOG Nov 09, 2022/5 min read

BLOG

How to Protect Advanced Chip Designs from Security Breaches

By Ian Land

Tags: Aerospace & Government, Silicon Lifecycle Management, Prototyping, Chip Design Insights, Simulation, Design, Emulation, Silicon IP, Verification, Formal Verification

BLOG Sep 04, 2022/1 min read

BLOG

Synopsys VCS and VIP By-the-Minute

By Verification Expert

Tags: Verification Central, Cloud, Simulation, Verification IP, Verification

Enhancing Chip Verification with AI and Machine Learning

BLOG Jul 12, 2022/4 min read

BLOG

Enhancing Chip Verification with AI and Machine Learning

By Rob van Blommestein

Tags: Multi-Die, Static Verification, AI & Machine Learning, Product Spotlight, Debug, Chip Design Insights, Simulation, HPC, Data Center, Verification, Formal Verification

Fault Simulation Techniques for Growing Chip Complexity

BLOG Jun 01, 2022/6 min read

BLOG

Fault Simulation Techniques for Growing Chip Complexity

By Brian Davenport, Rimpy Chugh

Tags: Customer Spotlight, Aerospace & Government, Debug, Chip Design Insights, Simulation, Automotive, Verification

Boosting EDA Workloads with 3rd Gen AMD EPYC™ Processors

BLOG Mar 20, 2022/4 min read

BLOG

Boosting EDA Workloads with 3rd Gen AMD EPYC™ Processors

By Ramesh Narayanaswamy

Tags: Customer Spotlight, Debug, Chip Design Insights, Simulation, Verification

What is Clock Domain Crossing? - ASIC Design Challenges

BLOG Nov 22, 2021/7 min read

BLOG

What is Clock Domain Crossing? - ASIC Design Challenges

By Rimpy Chugh

Tags: Debug, Chip Design Insights, Simulation, Verification

Software-Enabled Full Chip Power Signoff & SoC Verification

BLOG Nov 03, 2021/5 min read

BLOG

Software-Enabled Full Chip Power Signoff & SoC Verification

By Godwin Maben

Tags: Chip Design Insights, Simulation, Emulation, Energy-Efficient SoCs, Verification

How Emulation Helps Find Power Bugs During SoC Verification

BLOG Jul 06, 2021/5 min read

BLOG

How Emulation Helps Find Power Bugs During SoC Verification

By Alex Wakefield

Tags: Static Verification, Chip Design Insights, Simulation, Design, Emulation, Energy-Efficient SoCs, Signoff, Verification, Virtual Prototyping, Formal Verification

Stories

Writers

Top Writers

Taruna Reddy

Rob van Blommestein

Rimpy Chugh

Browse by Tags

Quantum Computing: How Advances May Reshape Our Understanding of the World

Automotive Reckoning: Industry Leaders Discuss the Race to Redefine Car Development

Driving the Future of Automotive: How Synopsys and Tata Elxsi Are Powering Electronics Digital Twin (eDT) Adoption

RTL Signoff vs. Functional Signoff: What’s the Difference?

Using Synopsys VSO.ai to Accelerate Synopsys VIP and IP Coverage

Synopsys HAPS-200 and ZeBu-200 Expand the Industry’s Highest Performance Hardware-Assisted Verification Portfolio

The Journey of Coverage Closure

Interactive Debugging: Reduce Your Simulation Debug Turnaround Time

Running X-Propagation with Low-Power Simulation

Streamline Projects with Verdi and VCS Coverage Tools

How Imparé Leverages Chip Design Verification in the Cloud

How to Get High-Performance Simulation with Predictable Capacity Uplift in the Cloud

Enhancing Chip Design Simulation with AI

How to Achieve 2X Faster Waveform Dumping in Synopsys Verdi with VCS

How Formal Verification Tools Enhance SoC Simulation Coverage

How to Protect Advanced Chip Designs from Security Breaches

Synopsys VCS and VIP By-the-Minute

Enhancing Chip Verification with AI and Machine Learning

Fault Simulation Techniques for Growing Chip Complexity

Boosting EDA Workloads with 3rd Gen AMD EPYC™ Processors

What is Clock Domain Crossing? - ASIC Design Challenges

Software-Enabled Full Chip Power Signoff & SoC Verification

How Emulation Helps Find Power Bugs During SoC Verification

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