Class and Object-Oriented Programming
One of the biggest features introduced in SystemVerilog is the ability to write functional model in an object-oriented manner, i.e. using the class
construct. Although class
construct is not synthesizable unfortunately, class
provides a more software-oriented approach to model hardware behavior for verification. SystemVerilog supports the following object-oriented programming (OOP) practice: - Inheritance - Polymorphism
In addition to the normal OOP, SystemVerilog also allows type parametrization for the class (similar to templates in C++)
5.1 Class Definition and Syntax
The sy