Skip to content

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

3 Commits
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

fluxkit_drv8302_example

Standalone hardware-integration scaffold for a Fluxkit + DRV8302 firmware project.

Stack

  • embassy-stm32
  • probe-rs runner via .cargo/config.toml
  • defmt + RTT via defmt-rtt
  • panic-probe
  • Embassy-generated memory.x via embassy-stm32/memory-x
  • standalone flake.nix for an embedded-capable Rust dev shell
  • path dependencies back to the local Fluxkit workspace

Dev Shell

Open the example shell directly from this crate:

cd ~/Develop/fluxkit_drv8302_example
XDG_CACHE_HOME=/tmp/fluxkit-nix-cache nix develop

Current state

This crate now contains a concrete board-level fluxkit-hal implementation for the current NUCLEO-G431KB + AS5048A + DRV8302 wiring.

  • TIM1-based 3-PWM output for DRV8302 on PA8/PA9/PA10
  • ADC1 injected current sampling on PA0/PA1, triggered from TIM1 CC4
  • AS5048A SPI sensor on PB3/PB4/PB5 with dedicated PB0 chip select
  • AS5048A sampling requested by separate TIM6 update interrupts at 10 kHz
  • SPI1 encoder transfers run through a raw DMA IRQ state machine instead of blocking inside the timer ISR
  • direct-drive output sensing implemented by sharing the AS5048A path for both rotor and output
  • fixed placeholder sensors for bus voltage and winding temperature until real hardware is wired
  • startup current zeroing with bounded sample collection and span checks before higher-level control

Hardware Summary

Current hardware target:

  • ST NUCLEO-G431KB
  • AS5048A absolute encoder over SPI at 3.3 V
  • DRV8302 breakout in 3-PWM mode
  • Cubemars GL60 KV55
  • encoder-based PMSM/BLDC FOC

Control split:

  • MCU generates 3 independent PWM phase commands
  • DRV8302 handles gate drive and current-shunt amplification
  • AS5048A provides rotor angle over SPI
  • output sensing is currently assumed to be the same direct-drive axis as the rotor encoder

Pin Map

MCU pin Header Function
PB3 D13 AS5048A SPI SCK
PB4 D12 AS5048A SPI MISO
PB5 D11 AS5048A SPI MOSI
PB0 D3 AS5048A CS
PA8 D9 DRV8302 INH-A / PWM A
PA9 D1 DRV8302 INH-B / PWM B
PA10 D0 DRV8302 INH-C / PWM C
PA11 D10 DRV8302 nFAULT input
PA12 D2 DRV8302 EN_GATE output
PB7 D4 DRV8302 nOCTW input, optional
PA0 A0 DRV8302 SO-1 ADC input
PA1 A1 DRV8302 SO-2 ADC input

Important notes:

  • D0 and D1 are repurposed as PWM outputs, not UART
  • EN_GATE should stay low through early bring-up
  • nFAULT and nOCTW are active-low inputs
  • AS5048A chip select is a dedicated GPIO on PB0

DRV8302 Mode Pins

  • M_PWM tied high: 3-PWM mode
  • GAIN tied high: 40 V/V
  • M_OC tied high: latched shutdown OCP mode
  • OC_ADJ must be driven by an external threshold divider, not left floating

Current Sense

Assumed current-sense configuration:

  • dual shunt outputs: SO-1, SO-2
  • shunt resistance: 0.002 ohm
  • shunt amplifier gain: 40 V/V
  • ADC reference: 3.3 V
  • zero-current midpoint: 1.65 V

Conversion model:

  • Vout = 1.65 V + 0.08 * Iphase
  • Iphase = (Vout - 1.65) / 0.08

Implementation note:

  • ADC samples should be treated as signed current signals around the midpoint
  • this example now performs zero-current offset calibration at startup before higher-level control is enabled

Power Notes

  • NUCLEO 3V3 powers AS5048A and DRV8302 logic/mode pins
  • external PSU powers the DRV8302 motor bus
  • MCU ground, encoder ground, DRV logic ground, and motor PSU negative must share a common ground
  • do not power the motor stage from NUCLEO 3V3 or 5V

Startup Sequence

Recommended bring-up order:

  1. keep EN_GATE low
  2. initialize clocks, GPIO, ADC, timers, and SPI
  3. verify AS5048A communication
  4. enable PWM in neutral and assert EN_GATE
  5. calibrate SO-1 / SO-2 zero-current offsets
  6. verify encoder/current/fault heartbeat while PWM remains neutral
  7. enable higher-level control or calibration once hardware checks are clean
  8. continuously monitor nFAULT and optionally nOCTW

Default assumptions

  • MCU family: STM32G4
  • MCU: STM32G431KB
  • default chip runner: STM32G431KBTx
  • default target: thumbv7em-none-eabihf
  • linker memory layout comes from Embassy's generated memory.x

Suggested next files

  • src/board.rs
  • src/inverter.rs
  • src/sensors.rs
  • src/runtime.rs
  • src/main.rs

Current firmware entrypoint

src/main.rs now exercises the board-level HAL implementation:

  • brings up TIM1 center-aligned 3-PWM
  • configures ADC1 injected conversions from TIM1 CC4
  • brings up the AS5048A SPI encoder path at 5 MHz
  • uses TIM6_DAC as a 10 kHz encoder sample launch source
  • advances AS5048A reads from DMA1_CHANNEL1 / DMA1_CHANNEL2 IRQs
  • enables neutral PWM and asserts DRV8302 EN_GATE
  • runs a bounded idle SO-1 / SO-2 zeroing routine with fresh-sample and span checks
  • keeps PWM neutral while logging board diagnostics at 1 Hz
  • leaves Fluxkit motor calibration disabled until hardware validation is complete
  • the dormant motor-calibration path is already updated for the new Fluxkit API and uses a PLL rotor estimator when re-enabled

Current software assumptions:

  • rotor and output sensors are the same physical AS5048A signal path
  • bus voltage is currently a fixed 20 V placeholder value
  • winding temperature is currently a fixed placeholder value

Note:

  • PB3 / D13 is also the NUCLEO user LED pin when SB15 connects the LED path
  • during encoder reads, that pin is used as SPI clock, not as a user LED

About

No description, website, or topics provided.

Resources

Stars

Watchers

Forks

Releases

Packages

Contributors

Languages